Table 1. Pin functions (continued)

Pin #

Default Pin

Function1

Pin Function

#2

Pin Function

#3

Description

16

RGPIO6

AN0-

TPMCH0

RGPIO6 / ADC Input 0 / TPM Channel 0

17

RGPIO7

AN1+

TPMCH1

RGPIO7 / ADC Input 1 / TPM Channel 1

18

SCLK1

RGPIO10

master queued SPI clock / RGPIO10

19

MOSI1

RGPIO11

master queued SPI Master Output Slave Input / RGPIO11

20

MISO1

RGPIO12

master queued SPI Master Input Slave Output / RGPIO12

21

SSB1

RGPIO13

master queued SPI slave select / RGPIO13

22

Analog power

235

RGPIO8

PDB_B

RGPIO8 / PDB_B

24

Analog ground

1. Default Pin Function 1 represents the reset state of the device. Pin functions may be changed via the SIM pin mux-

control registers. Drive strength and pullup controls are programmed by the port control registers.

2. SCL1 is available for use on pin (RGPIO14) only when SIM_PMCR1[A2] is not equal to "01". That setting would

enable it for pin 11 (RGPIO2).

3. SDA1 is available for use on pin (RGPIO15) only when SIM_PMCR1[A3] is not equal to "01". That setting would

enable it for pin 12 (RGPIO3).

4. RESETB defaults to input only, but can be configured as an open-drain, bidirectional pin.

4.2.1 Pin function description

Descriptions of the pin functions available on this device are provided in this section.

Sixteen of the device pins are multiplexed with Rapid GPIO (RGPIO) functions. The

Default Pin Function column of Table 1 lists which function is active when the device

exits the reset state. User firmware can use the Pin Mux Control registers in the

System Integration Module (SIM) to change pin assignments for these pins after reset.

power domain from other pins is not recommended.

supply this power domain from other pins is not recommended.

General Description

Xtrinsic FXLC95000CL Intelligent, Motion-Sensing Platform, Rev1.2, 8/2013.

9

Freescale Semiconductor, Inc.