AD9754ARURL7 datasheet(13/24 Pages) AD

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AD9754

–13–

REV. A

INPUT CLOCK AND DATA TIMING RELATIONSHIP

SNR in a DAC is dependent on the relationship between the

position of the clock edges and the point in time at which the

input data changes. The AD9754 is positive edge triggered, and

so exhibits SNR sensitivity when the data transition is close to

this edge. In general, the goal when applying the AD9754 is to

make the data transitions close to the negative clock edge. This

becomes more important as the sample rate increases. Figure 23

shows the relationship of SNR to clock placement.

TIME (ns) OF DATA CHANGE RELATIVE TO

RISING CLOCK EDGE

–8

–6

–4

–2

468

FS = 125MSPS

FS = 65MSPS

Figure 23. SNR vs. Clock Placement @ fOUT = 10 MHz

SLEEP MODE OPERATION

The AD9754 has a power-down function that turns off the

output current and reduces the supply current to less than

8.5 mA over the specified supply range of 2.7 V to 5.5 V and

temperature range. This mode can be activated by applying a

logic level “1” to the SLEEP pin. This digital input also con-

tains an active pull-down circuit that ensures the AD9754 re-

mains enabled if this input is left disconnected. The AD9754

takes less than 50 ns to power down and approximately 5

µs to

power back up.

POWER DISSIPATION

The power dissipation, PD, of the AD9754 is dependent on

several factors, including: (1) AVDD and DVDD, the power

supply voltages; (2) IOUTFS, the full-scale current output; (3)

fCLOCK, the update rate; and (4) the reconstructed digital input

waveform. The power dissipation is directly proportional to the

analog supply current, IAVDD, and the digital supply current,

IDVDD. IAVDD is directly proportional to IOUTFS, as shown in

Figure 24, and is insensitive to fCLOCK.

Conversely, IDVDD is dependent on both the digital input wave-

form, fCLOCK, and digital supply DVDD. Figures 25 and 26

show IDVDD as a function of full-scale sine wave output ratios

(fOUT/fCLOCK) for various update rates with DVDD = 5 V and

DVDD = 3 V, respectively. Note, how IDVDD is reduced by more

than a factor of 2 when DVDD is reduced from 5 V to 3 V.

IOUTFS – mA

220

Figure 24. IAVDD vs. IOUTFS

RATIO (fCLOCK/fOUT)

0.01

0.1

5MSPS

25MSPS

50MSPS

100MSPS

125MSPS

Figure 25. IDVDD vs. Ratio @ DVDD = 5 V

RATIO (fCLOCK/fOUT)

0.01

0.1

5MSPS

25MSPS

50MSPS

100MSPS

125MSPS

Figure 26. IDVDD vs. Ratio @ DVDD = 3 V

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