PIC16F1507T-ISOSQTP datasheet(72/266 Pages) MICROCHIP

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Preliminary

DS41586A-page 72

PIC16(L)F1507

7.6.7

PIR3 REGISTER

The PIR3 register contains the interrupt flag bits, as

shown in Register 7-7.

Note:

Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit or the Global

Enable bit, GIE, of the INTCON register.

User

software

should

ensure

the

appropriate interrupt flag bits are clear prior

to enabling an interrupt.

PIR3: PERIPHERAL INTERRUPT REQUEST REGISTER 3

U-0

R/W-0/0

—

CLC2IF

CLC1IF

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

u = Bit is unchanged

x = Bit is unknown

-n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set

‘0’ = Bit is cleared

bit 7-2

Unimplemented:

Read as ‘0’

bit 1

CLC2IF:

Configurable Logic Block 2 Interrupt Flag bit

= Interrupt is pending

= Interrupt is not pending

bit 0

CLC1IF:

Configurable Logic Block 1 Interrupt Flag bit

= Interrupt is pending

= Interrupt is not pending

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