PIC16F1507T-ESSQTP datasheet(71/266 Pages) MICROCHIP

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PIC16(L)F1507

DS41586A-page 71

Preliminary

 2011 Microchip Technology Inc.

7.6.6

PIR2 REGISTER

The PIR2 register contains the interrupt flag bits, as

shown in Register 7-6.

Note:

Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit or the Global

Interrupt Enable bit, GIE, of the INTCON

appropriate interrupt flag bits are clear prior

to enabling an interrupt.

PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2

U-0

R/W-0/0

U-0

—

NCO1IF

—

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

u = Bit is unchanged

x = Bit is unknown

-n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set

‘0’ = Bit is cleared

bit 7-3

Unimplemented:

Read as ‘0’

bit 2

NCO1IF:

Numerically Controlled Oscillator Flag bit

= Interrupt is pending

= Interrupt is not pending

bit 1-0

Unimplemented:

Read as ‘0’

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