AT90USB646 datasheet(73/456 Pages) ATMEL

73 / 456 page

7593L–AVR–09/12

AT90USB64/128

11.2.2

Toggling the pin

Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn.

Note that the SBI instruction can be used to toggle one single bit in a port.

11.2.3

Switching between input and output

When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn}

= 0b11), an intermediate state with either pull-up enabled {DDxn, PORTxn} = 0b01) or output

low ({DDxn, PORTxn} = 0b10) occurs. Normally, the pull-up enabled state is fully acceptable, as

a high-impedant environment will not notice the difference between a strong high driver and a

pull-up. If this is not the case, the PUD bit in the MCUCR Register can be set to disable all pull-

ups in all ports.

Switching between input with pull-up and output low generates the same problem. The user

must use either the tri-state ({DDxn, PORTxn} = 0b00) or the output high state ({DDxn, PORTxn}

= 0b11) as an intermediate step.

Table 11-1 summarizes the control signals for the pin value.

11.2.4

Reading the pin value

Independent of the setting of Data Direction bit DDxn, the port pin can be read through the

PINxn Register bit. As shown in Figure 11-2 on page 72, the PINxn Register bit and the preced-

ing latch constitute a synchronizer. This is needed to avoid metastability if the physical pin

changes value near the edge of the internal clock, but it also introduces a delay. Figure 11-3 on

page 74 shows a timing diagram of the synchronization when reading an externally applied pin

value. The maximum and minimum propagation delays are denoted t

pd, max and tpd,min

respectively.

Table 11-1.

Port pin configurations.

DDxn

PORTxn

PUD

(in MCUCR)

I/O

Pull-up

Comment

Input

Tri-state (Hi-Z)

Input

Yes

Pxn will source current if ext. pulled low

Input

Tri-state (Hi-Z)

Output

Output Low (Sink)

Output

Output High (Source)

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