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IMX51 bảng dữ liệu(PDF) 75 Page - Freescale Semiconductor, Inc

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Giải thích chi tiết về linh kiện  i.MX51 Applications Processors for Consumer and Industrial Products
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IMX51 bảng dữ liệu(HTML) 75 Page - Freescale Semiconductor, Inc

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Electrical Characteristics
i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 6
Freescale Semiconductor
75
4.7.1.2
CSPI Slave Mode Timing
Figure 39 depicts the timing of CSPI in Slave mode. Table 66 lists the CSPI Slave Mode timing
characteristics.
Figure 39. CSPI Slave Mode Timing Diagram
CS5
SSx Lead Time (Slave Select
setup time)
tSCS
26
—
ns
CS6
SSx Lag Time (SS hold time)
tHCS
26
—
ns
CS7
MOSI Propagation Delay
(CLOAD =20pF)
tPDmosi
–1
21
ns
CS8
MISO Setup Time
tSmiso
5—
ns
CS9
MISO Hold Time
tHmiso
5—
ns
CS10
RDY to SSx Time2
tSDRY
5—
ns
1 See specific I/O AC parameters Section 4.5, “I/O AC Parameters”
2 SPI_RDY is sampled internally by ipg_clk and is asynchronous to all other CSPI signals.
Table 66. CSPI Slave Mode Timing Parameters
ID
Parameter
Symbol
Min
Max
Unit
CS1
SCLK Cycle Time
tclk
60
—
ns
CS2
SCLK High or Low Time
tSW
26
—
ns
CS4
SSx pulse width
tCSLH
26
—
ns
CS5
SSx Lead Time (SS setup time)
tSCS
26
—
ns
CS6
SSx Lag Time (SS hold time)
tHCS
26
—
ns
CS7
MOSI Setup Time
tSmosi
5—
ns
Table 65. CSPI Master Mode Timing Parameters (continued)
ID
Parameter
Symbol
Min
Max
Unit
CS1
CS7
CS8
CS2
CS2
CS4
CS6
CS5
CS9
SCLK
SSx
MISO
MOSI



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