TDA9331H datasheet(39/56 Pages) NXP

39 / 56 page

2002 Jun 04

Philips Semiconductors

Preliminary speciﬁcation

I2C-bus controlled TV display processors

TDA933xH series

handbook, full pagewidth

MGS897

0.75

µs

2.35

µs

2.40

µs

5.5

µs

mid blank = mid flyback

37 LLC = 2.67

µs

22 LLC = 1.59

µs

HD input

HSHIFT

2fH NTSC

signal

(fH = 31.47 kHz)

CLP pulse

counter

blanking

0.606

µs

0.592

µs

1.993

µs

3.784

µs

50 ns

mid blank = mid flyback

18 LLC = 1.22

µs

HD input

HDTV

signal

(fH = 33.75 kHz)

CLP pulse

0.592

µs

15 LLC = 1.01

µs

counter

blanking

(a) Timing in 2 fH TV mode (HDTV = 0, HDCL = 0)

(b) Timing in HDTV mode (HDTV = 1, HDCL = 1)

HSHIFT

40 LLC = 2.69

µs

+ 14 LLC

− 16 LLC

40 LLC = 2.89

µs

+ 14 LLC

− 16 LLC

Fig.11 Timing of clamp pulse and line blanking in 2fH TV mode and HDTV mode.

Video signals are shown as illustration only. All horizontal timing signals in the IC are solely related to the start of the HD pulse

that is applied to the IC.

All horizontal timing signals are generated with the help of the internal line locked clock (LLC). One line period is always divided

into 440 line locked clock pulses. Time periods depicted in the figure are only valid for line frequencies mentioned.

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