74HC75 datasheet(2/20 Pages) NXP

2 / 20 page

9397 750 13816

Product data sheet

Rev. 03 — 12 November 2004

2 of 20

Philips Semiconductors

74HC75

Quad bistable transparant latch

Quick reference data

[1]

CPD is used to determine the dynamic power dissipation (PD in µW).

PD =CPD × VCC2 × fi × N+ ∑(CL × VCC2 × fo) where:

fi = input frequency in MHz;

fo = output frequency in MHz;

CL = output load capacitance in pF;

VCC = supply voltage in V;

N = number of inputs switching;

∑(C

L × VCC

× f

o) = sum of outputs.

Ordering information

Table 1:

Quick reference data

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

tPHL, tPLH

propagation delay

CL =15pF;

VCC =5V

nD to nQ, nQ

LEnn to nQ, nQ

input capacitance

3.5

CPD

power dissipation

capacitance per latch

VI = GND to VCC

[1] -42

Table 2:

Ordering information

Type number

Package

Temperature range

Name

Description

Version

74HC75N

−40 °C to +125 °C

DIP16

plastic dual in-line package; 16 leads (300 mil)

SOT38-4

74HC75D

−40 °C to +125 °C

SO16

plastic small outline package; 16 leads;

body width 3.9 mm

SOT109-1

74HC75DB

−40 °C to +125 °C

SSOP16

plastic shrink small outline package; 16 leads;

body width 5.3 mm

SOT338-1

74HC75PW

−40 °C to +125 °C

TSSOP16

plastic thin shrink small outline package;

16 leads; body width 4.4 mm

SOT403-1

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