LP3906 datasheet(26/47 Pages) TI

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LP3906

SNVS456M – AUGUST 2006 – REVISED MAY 2013

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INTERRUPT STATUS REGISTER (ISRA) 0X02

This register informs the user of the temperature status of the chip.

D7-2

Name

—

Temp 125°C

—

Access

—

Data

Reserved

Status bit for thermal warning PMIC T>125°C

Reserved

0 – PMIC Temp. < 125°C

1 – PMIC Temp. > 125°C

Reset

CONTROL 1 REGISTER (SCR1) 0X07

This register allows the user to select the preset delay sequence for power-on timing, to switch between PFM

and PWM mode for the bucks, and also to select between an internal and external clock for the bucks.

The external LDO and SW enables should be pulled LOW to allow the blocks to sequence correctly through

assertion of the EN_T pin.

D6-4

Name

—

EN_DLY

—

FPWM2

FPWM1

ECEN

Access

—

R/W

—

R/W

Data

Reserved

Selects the preset

Reserved

Buck 2 PWM /PFM

Buck 1 PWM /PFM

External Buck Clock

delay sequence from

Mode select

Select

EN_T assertion

0 – Auto Switch PFM -

0 – Internal 2 MHz

(shown below)

PWM operation

Oscillator clock

1 – PWM Mode Only

1 – External 13 MHz

Oscillator clock

Reset

010

EN_DLY PRESET DELAY SEQUENCE AFTER EN_T ASSERTION

Delay (ms)

EN_DLY<2:0>

Buck1

Buck2

LDO1

LDO2

000

001

1.5

010

1.5

011

1.5

100

1.5

101

1.5

110

1.5

111

BUCK AND LDO OUTPUT VOLTAGE ENABLE REGISTER (BKLDOEN) – 0X10

This register controls the enables for the Bucks and LDOs.

Name

—

LDO2EN

—

LDO1EN

—

BK2EN

—

BK1EN

Access

—

R/W

—

R/W

—

R/W

—

R/W

Data

Reserved

0 – Disable

Reserved

0 – Disable

Reserved

0 – Disable

Reserved

0 – Disable

1 – Enable

Reset

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