TLC7528C, TLC7528E, TLC7528I

DUAL 8BIT MULTIPLYING

DIGITALTOANALOG CONVERTERS

SLAS062E − JANUARY 1987 − REVISED NOVEMBER 2008

8

POST OFFICE BOX 655303

APPLICATION INFORMATION

+

−

R11

5 k

Ω

A2

VOA

DACB

R6

20 k

Ω

(see Note B)

VOB

AGND

A1

DGND

A4

R3

(see Note A)

R1

(see Note A)

AGND

C1

(see Note C)

C2

(see Note C)

R2 (see Note A)

R4 (see Note A)

AGND

OUTB

RFBB

AGND

OUTA

5

VDD

17

7

14

DACA/

DACB

DB0

DB7

8

8

8

8

REFB

RFBA

DACA

CS

WR

16

15

6

A3

R10

20 k

Ω

(see Note B)

Latch

Input

Buffer

Control

Logic

Latch

R8

20 k

Ω

R7

10 k

Ω

(see Note B)

R9

10 k

Ω

(see Note B)

R11

5 k

Ω

R5

20 k

Ω

VI(A)

±10 V

VI(B)

±10 V

NOTES: A. R1, R2, R3, and R4 are used only if gain adjustment is required. See table in Figure 3 for recommended values. Adjust R1 for

VOA = 0V with code 10000000 in DACA latch. Adjust R3 for VOB = 0V with 10000000 in DACB latch.

B. Matching and tracking are essential for resistor pairs R6, R7, R9, and R10.

C. C1 and C2 phase compensation capacitors (10pF to 15pF) may be required if A1 and A3 are high-speed amplifiers.

Figure 4. Bipolar Operation (4-Quadrant Operation)

Table 1. Unipolar Binary Code

Table 2. Bipolar (Offset Binary) Code

DAC LATCH CONTENTS

ANALOG OUTPUT

DAC LATCH CONTENTS

ANALOG OUTPUT

MSB

LSB†

ANALOG OUTPUT

MSB

LSB‡

ANALOG OUTPUT

1 1 1 1 1 1 1 1

1 0 0 0 0 0 0 1

1 0 0 0 0 0 0 0

0 1 1 1 1 1 1 1

0 0 0 0 0 0 0 1

0 0 0 0 0 0 0 0

−VI (255/256)

−VI (129/256)

−VI (128/256) = − Vi/2

−VI (127/256)

−VI (1/256)

−VI (0/256) = 0

1 1 1 1 1 1 1 1

1 0 0 0 0 0 0 1

1 0 0 0 0 0 0 0

0 1 1 1 1 1 1 1

0 0 0 0 0 0 0 1

0 0 0 0 0 0 0 0

VI (127/128)

VI (1/128)

0V

−VI (1/128)

−VI (127/128)

−VI (128/128)

† 1LSB = (2−8)VI

‡ 1LSB = (2−7)VI