DIX4192 datasheet(3/64 Pages) TI1

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ELECTRICAL CHARACTERISTICS: General, DIR, and DIT

DIX4192

SBFS031C – JANUARY 2006 – REVISED JUNE 2006

All specifications are at TA = +25°C, VDD18 = +1.8V, VDD33 = +3.3V, VIO = +3.3V, and VCC = +3.3V, unless otherwise noted.

DIX4192

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

DIGITAL I/O CHARACTERISTICS

(All I/O pins except line receivers and line driver)

High-level input voltage, VIH

0.7 × VIO

VIO

Low-level input voltage, VIL

0.3 × VIO

High-level input current, IIH

0.5

µA

Low-level input current, VIL

0.5

µA

High-level output voltage, VOH

IO = –4mA

0.8 × VIO

VIO

Low-level output voltage, VOL

IO = +4mA

0.2 × VIO

Input capacitance, CIN

LINE RECEIVER INPUTS

(RX1+, RX1–, RX2+, RX2–, RX3+, RX3–, RX4+, RX4–)

Voltage across a given

Differential input sensitivity, VTH

150

200

differential input pair

Input hysteresis, VHY

150

LINE DRIVER OUTPUTS

(TX+, TX–)

Differential output voltage, VTXO

RL = 110Ω Across TX+ and TX–

5.4

VPP

MASTER CLOCK INPUT

Master clock input (MCLK) frequency, fMCLK

27.7

MHz

Master clock input (MCLK) duty cycle, fMCLKD

DIGITAL AUDIO INTERFACE RECEIVER (DIR)

PLL lock range

216

kHz

Reference clock input (RXCKI) frequency, fRXCKI

3.5

27.7

MHz

Reference clock input (RXCKI) duty cycle, fRXCKID

Recovered clock output (RXCKO) frequency, fRXCKO

3.5

27.7

MHz

Recovered clock output (RXCKO) duty cycle, fRXCKOD

Recovered clock output (RXCKO) intrinsic jitter

Measured cycle-to-cycle

250

ps RMS

DIGITAL AUDIO INTERFACE TRANSMITTER (DIT)

Intrinsic output jitter

Measured cycle-to-cycle

200

ps RMS

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