DSPIC30F2011AT-30ESLASHPF datasheet(131/228 Pages) MICROCHIP

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DS70117F-page 129

dsPIC30F6011/6012/6013/6014

18.3.7

BIT CLOCK GENERATOR

The DCI module has a dedicated 12-bit time base that

produces the bit clock. The bit clock rate (period) is set

by writing a non-zero 12-bit value to the BCG<11:0>

control bits in the DCICON3 SFR.

When the BCG<11:0> bits are set to zero, the bit clock

will be disabled. If the BCG<11:0> bits are set to a non-

zero value, the bit clock generator is enabled. These

bits should be set to ‘0’ and the CSCKD bit set to ‘1’ if

the serial clock for the DCI is received from an external

device.

The formula for the bit clock frequency is given in

Equation 18-2.

EQUATION 18-2:

BIT CLOCK FREQUENCY

The required bit clock frequency will be determined by

the system sampling rate and frame size. Typical bit

clock frequencies range from 16x to 512x, the con-

verter sample rate depending on the data converter

and the communication protocol that is used.

To achieve bit clock frequencies associated with com-

mon audio sampling rates, the user will need to select

a crystal frequency that has an ‘even’ binary value.

Examples of such crystal frequencies are listed in

Table 18-1.

TABLE 18-1:

DEVICE FREQUENCIES FOR COMMON CODEC CSCK FREQUENCIES

FBCK =

FCY

(BCG + 1)

•

FS (KHz)

FCSCK/FS

FCSCK (MHz)(1)

FOSC (MHZ)PLL

FCY (MIPS)

BCG(2)

256

2.048

8.192

256

3.072

6.144

12.288

1.024

8.192

16.384

44.1

1.4112

5.6448

11.2896

3.072

6.144

24.576

Note 1: When the CSCK signal is applied externally (CSCKD = 1), the external clock high and low times must meet

the device timing requirements.

2: When the CSCK signal is applied externally (CSCKD = 1), the BCG<11:0> bits have no effect on the

operation of the DCI module.

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