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DSPIC30F2011AT-30E/PF bảng dữ liệu(PDF) 95 Page - Microchip Technology |
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DSPIC30F2011AT-30E/PF bảng dữ liệu(HTML) 95 Page - Microchip Technology |
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95 / 228 page  © 2006 Microchip Technology Inc. DS70117F-page 93 dsPIC30F6011/6012/6013/6014 14.3 Slave Select Synchronization The SSx pin allows a Synchronous Slave mode. The SPI must be configured in SPI Slave mode with SSx pin control enabled (SSEN = 1). When the SSx pin is low, transmission and reception are enabled and the SDOx pin is driven. When SSx pin goes high, the SDOx pin is no longer driven. Also, the SPI module is re- synchronized, and all counters/control circuitry are reset. Therefore, when the SSx pin is asserted low again, transmission/reception will begin at the MSb even if SSx had been de-asserted in the middle of a transmit/receive. 14.4 SPI Operation During CPU Sleep Mode During Sleep mode, the SPI module is shutdown. If the CPU enters Sleep mode while an SPI transaction is in progress, then the transmission and reception is aborted. The transmitter and receiver will stop in Sleep mode. However, register contents are not affected by entering or exiting Sleep mode. 14.5 SPI Operation During CPU Idle Mode When the device enters Idle mode, all clock sources remain functional. The SPISIDL bit (SPIxSTAT<13>) selects if the SPI module will stop or continue on Idle. If SPISIDL = 0, the module will continue to operate when the CPU enters Idle mode. If SPISIDL = 1, the module will stop when the CPU enters Idle mode. |
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