ADS4229IRGC25 datasheet(13/67 Pages) TI1

13 / 67 page

ADS4229

www.ti.com

SBAS550B – JUNE 2011 – REVISED AUGUST 2012

Pin Descriptions (LVDS Mode)

PIN NUMBER

PIN NAME

# OF PINS

FUNCTION

DESCRIPTION

1, 48

DRVDD

Input

Output buffer supply

Serial interface RESET input.

When using the serial interface mode, the internal registers must be initialized

through a hardware RESET by applying a high pulse on this pin or by using the

RESET

Input

software reset option; refer to the Serial Interface Configuration section.

In parallel interface mode, the RESET pin must be permanently tied high. SCLK

and SEN are used as parallel control pins in this mode. This pin has an internal

150-k

Ω pull-down resistor.

This pin functions as a serial interface clock input when RESET is low. It controls

SCLK

Input

the low-speed mode selection when RESET is tied high; see Table 6 for detailed

information. This pin has an internal 150-k

Ω pull-down resistor.

SDATA

Input

Serial interface data input; this pin has an internal 150-k

Ω pull-down resistor.

This pin functions as a serial interface enable input when RESET is low. It

controls the output interface and data format selection when RESET is tied high;

SEN

Input

see Table 7 for detailed information. This pin has an internal 150k

Ω pull-up

resistor to AVDD.

16, 22, 33, 34

AVDD

Input

Analog power supply

17, 18, 21, 24, 27, 28,

AGND

Input

Analog ground

31, 32

INP_B

Input

Differential analog positive input, channel B

INM_B

Input

Differential analog negative input, channel B

This pin outputs the common-mode voltage (0.95 V) that can be used externally

VCM

Output

to bias the analog input pins

CLKP

Input

Differential clock positive input

CLKM

Input

Differential clock negative input

INP_A

Input

Differential analog positive input, channel A

INM_A

Input

Differential analog negative input, channel A

CTRL1

Input

Digital control input pins. Together, they control the various power-down modes.

CTRL2

Input

Digital control input pins. Together, they control the various power-down modes.

CTRL3

Input

Digital control input pins. Together, they control the various power-down modes.

49, PAD

DRGND

Input

Output buffer ground

CLKOUTP

Output

Differential output clock, true

CLKOUTM

Output

Differential output clock, complement

This pin functions as a serial interface register readout when the READOUT bit is

SDOUT

Output

enabled. When READOUT = 0, this pin is put into a high-impedance state.

Refer to Figure 5

DA0P, DA0M

Output

Channel A differential output data pair, D0 and D1 multiplexed

Refer to Figure 5

DA2P, DA2M

Output

Channel A differential output data D2 and D3 multiplexed

Refer to Figure 5

DA4P, DA4M

Output

Channel A differential output data D4 and D5 multiplexed

Refer to Figure 5

DA6P, DA6M

Output

Channel A differential output data D6 and D7 multiplexed

Refer to Figure 5

DA8P, DA8M

Output

Channel A differential output data D8 and D9 multiplexed

DA10P,

Refer to Figure 5

Output

Channel A differential output data D10 and D11 multiplexed

DA10M

DA12P,

Refer to Figure 5

Output

Channel A differential output data D12 and D13 multiplexed

DA12M

Refer to Figure 5

DB0P, DB0M

Output

Channel B differential output data pair, D0 and D1 multiplexed

Refer to Figure 5

DB2P, DB2M

Output

Channel B differential output data D2 and D3 multiplexed

Refer to Figure 5

DB4P, DB4M

Output

Channel B differential output data D4 and D5 multiplexed

Refer to Figure 5

DB6P, DB6M

Output

Channel B differential output data D6 and D7 multiplexed

Refer to Figure 5

DB8P, DB8M

Output

Channel B differential output data D8 and D9 multiplexed

DB10P,

Refer to Figure 5

Output

Channel B differential output data D10 and D11 multiplexed

DB10M

DB12P,

Refer to Figure 5

Output

Channel B differential output data D12 and D13 multiplexed

DB12M

Refer to Figure 5

—

Do not connect, must be floated

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