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AS5013 bảng dữ liệu(PDF) 22 Page - ams AG

tên linh kiện AS5013
Giải thích chi tiết về linh kiện  Low Power Integrated Hall IC for Human Interface Applications
PDF  32 Pages
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nhà sản xuất  AMSCO [ams AG]
Trang chủ  http://www.ams.com
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AS5013 bảng dữ liệu(HTML) 22 Page - ams AG

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Revision 1.11
22 - 32
AS5013
Datasheet - I² C Registers
8.11 Control Register 2 (2Eh)
Figure 17. Magnet Configuration
Note:
In order to know the polarity of the magnet without any testing device, please refer to Registers Initialization on page 24.
8.12 Hall Element Direct Read Registers (16h to 29h)
Each hall element C1..C5 can be read independently, after each interrupt (data ready).
One hall element value consists of two 12-bit signed-registers: Cx_neg and Cx_pos. For each conversion cycle (i.e. after a readout or Y_res in
idle mode, or at each time-based conversion cycle in Low Power mode), each hall element is read twice: With normal spin (result Cx_pos) and
then with inverted spin (result Cx_neg) in order to remove any hall voltage offset from the hall elements.
The formula to read any hall element Cx:
Cx = (Cx_pos – Cx_neg) / 2
(EQ 1)
Where:
Cx_pos = (Cx_pos[11:8] << 8) | Cx_pos[7:0]
Cx_neg = (Cx_neg[11:8] << 8) | Cx_neg[7:0]
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Test
Test
Test
ext_clk_en
use_static_offset EN_offset_comp
inv_spinning
pptrim_en
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset value: 1000 0100
Bit
Bit Description
7
Test bit. Must configured ‘1’.
6:4
Test bit. Must configured ‘000’.
3
Test bit. Must configured ‘0’.
2
Test bit. Must configured ‘1’.
1
Magnet Polarity bit. Must be set after power up, depending on how the magnet is placed (see Figure 17).
0
Test bit. Must configured ‘0’.
S
N
S
N
S
N
S
N
Magnet configuration 2
Bit Inv_spinning = 0 (default)
AS5013
AS5013
AS5013
AS5013
Magnet configuration 1
Bit Inv_spinning = 1
Magnet configuration 3
Magnet configuration 4
(e.g. EasyPoint modules)



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