HCPL-0708 datasheet(10/12 Pages) AVAGO

10 / 12 page

Application Information

Bypassing and PC Board Layout

The HCPL-0708 optocoupler is extremely easy to use. No

external interface circuitry is required because the HCPL-

0708 uses high-speed CMOS IC technology allowing

CMOS logic to be connected directly to the inputs and

outputs.

Figure 6. Recommended printed circuit board layout.

Figure 7. Recommended printed circuit board layout.

Propagation Delay, Pulse-Width Distortion and Propagation

Delay Skew

Propagation Delay is a figure of merit which describes

how quickly a logic signal propagates through a sys-

tem. The propagation delay from low to high (tPLH) is the

amount of time required for an input signal to propagate

to the output, causing the output to change from low

Figure 8.

INPUT

tPLH

tPHL

OUTPUT

10%

90%

10%

VOH

VOL

0 mA

50%

12 mA

2.5 V CMOS

GND

VDD

C1, C2 = 0.01 µF TO 0.1 µF

VDD

GND

C1, C2 = 0.01 µF TO 0.1 µF

As shown in Figure 6, the only external component re-

quired for proper operation is the bypass capacitor. Ca-

pacitor values should be between 0.01 µF and 0.1 µF. For

each capacitor, the total lead length between both ends

of the capacitor and the power-supply pins should not

exceed 20 mm. Figure 7 illustrates the recommended

printed circuit board layout for the HPCL-0708.

to high. Similarly, the propagation delay from high to

low (tPHL) is the amount of time required for the input

signal to propagate to the output, causing the output to

change from high to low. See Figure 8.

HCPL-0708 bảng dữ liệu(PDF) 10 Page - AVAGO TECHNOLOGIES LIMITED

HCPL-0708 bảng dữ liệu(HTML) 10 Page - AVAGO TECHNOLOGIES LIMITED

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12

bảng dữ liệu tải về

Link URL