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Data Sheet
ADAS1000/ADAS1000-1/ADAS1000-2
Rev. A | Page 15 of 80
Figure 10. ADAS1000-2 Companion 64-Lead LQFP Pin Configuration
Figure 11. ADAS1000-2 Companion 56-Lead LFCSP Pin Configuration
Table 9. Pin Function Descriptions
ADAS1000
ADAS1000-1
ADAS1000-2
Mnemonic
Description
LQFP
LFCSP
LFCSP
LQFP
LFCSP
18, 23,
58, 63
15, 20,
51, 56
15, 20, 51, 56
18, 23,
58, 63
15, 20,
51, 56
AVDD
Analog Supply. See recommendations for bypass capacitors in the Power
Supply, Grounding, and Decoupling Strategy section.
35, 46
30, 41
30, 41
35, 46
30, 41
IOVDD
Digital Supply for Digital Input/Output Voltage Levels. See
recommendations for bypass capacitors in the Power Supply, Grounding,
and Decoupling Strategy section.
26, 55
23, 48
23, 48
26, 55
23, 48
ADCVDD
Analog Supply for ADC. There is an on-chip linear regulator providing the
supply voltage for the ADCs. This pin is primarily provided for decoupling
purposes; however, the pin may also be supplied by an external 1.8 V
supply should the user wish to use a more efficient supply to minimize
power dissipation. In this case, use the VREG_EN pin tied to ground to
disable the ADCVDD and DVDD regulators. The ADCVDD pin should not
be used to supply other functions. See recommendations for bypass
capacitors in the Power Supply, Grounding, and Decoupling Strategy
section.
30, 51
27, 44
27, 44
30, 51
27, 44
DVDD
Digital Supply. There is an on-chip linear regulator providing the supply
voltage for the digital core. This pin is primarily provided for decoupling
purposes; however, the pin may also be overdriven supplied by an
external 1.8 V supply should the user wish to use a more efficient supply
to minimize power dissipation. In this case, use the VREG_EN pin tied to
ground to disable the ADCVDD and DVDD regulators. See
recommendations for bypass capacitors in the Power Supply, Grounding,
and Decoupling Strategy section.
2, 15,
24, 25,
56, 57
1, 14,
21, 22,
49, 50
1, 14, 21, 22,
49, 50
2, 15,
24, 25,
56, 57
1, 14, 21,
22, 49,
50
AGND
Analog Ground.
31, 34,
40, 47,
50
28, 29,
36, 42,
43
28, 29, 36, 42,
43
31, 34,
40, 47,
50
28, 29,
36, 42,
43
DGND
Digital Ground.
59
19
19
59
19
VREG_EN
Enables or disables the internal voltage regulators used for ADCVDD and
DVDD. Tie this pin to AVDD to enable or tie this pin to ground to disable
the internal voltage regulators.
10
6
6
ECG1_LA
Analog Input, Left Arm (LA).
11
5
5
ECG2_LL
Analog Input, Left Leg (LL).
12
4
4
ECG3_RA
Analog Input, Right Arm (RA).
13
3
3
ECG4_V1
Analog Input, Chest Electrode 1 or Auxiliary Biopotential Input (V1).
NOTES
1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.
DGND
IOVDD
GPIO0
GPIO1
GPIO2
GPIO3
DGND
CS
DRDY
SDI
SCLK
SDO
IOVDD
DGND
NC
NC
PIN 1
ADAS1000-2
64-LEAD LQFP
TOP VIEW
(Not to Scale)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19 20
21 22 23 24 25 26 27 28
29 30 31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
NC
NC
REFGND
REFOUT
REFIN
ECG1
ECG2
NC
AGND
ECG4
NC
AGND
NC
ECG5
NC
ECG3
NOTES
1. THE EXPOSED PADDLE IS ON THE TOP OF THE PACKAGE;
IT IS CONNECTED TO THE MOST NEGATIVE POTENTIAL, AGND.
2. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.
PIN 1
INDICATOR
1
AGND
2
NC
3
NC
4
NC
5
NC
6
REFGND
7
REFOUT 8
REFIN
9
ECG1
10
ECG2
11
ECG3
12
ECG4
13
ECG5
14
AGND
35
36
37
38
39
40
41
42
34
33
32
31
30
29
ADAS1000-2
56-LEAD LFCSP
TOP VIEW
(Not to Scale)
DGND
CS
DRDY
SDI
SCLK
SDO
IOVDD
DGND
GPIO3
GPIO2
GPIO1
GPIO0
IOVDD
DGND



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