ADR395AUJZ-R21 datasheet(14/20 Pages) AD

14 / 20 page

ADR391/ADR392/ADR395

Rev. H | Page 14 of 20

THEORY OF OPERATION

Band gap references are the high performance solution for low

supply voltage and low power voltage reference applications,

and the ADR391/ADR392/ADR395 are no exception. The

uniqueness of these devices lies in the architecture. As shown in

Figure 33, the ideal zero TC band gap voltage is referenced to

the output, not to ground. Therefore, if noise exists on the

ground line, it is greatly attenuated on VOUT. The band gap cell

consists of the PNP pair, Q51 and Q52, running at unequal

current densities. The difference in VBE results in a voltage with

a positive TC, which is amplified by a ratio of

R54

R58

2 ×

This PTAT voltage, combined with VBEs of Q51 and Q52,

produces a stable band gap voltage.

Reduction in the band gap curvature is performed by the ratio

of Resistors R44 and R59, one of which is linearly temperature

dependent. Precision laser trimming and other patented circuit

techniques are used to further enhance the drift performance.

SHDN

R60

Q51

R54

R61

R53

Q52

R58

R59

R44

R48

R49

GND

VIN

VOUT (FORCE)

VOUT (SENSE)

Figure 33. Simplified Schematic

DEVICE POWER DISSIPATION CONSIDERATIONS

The ADR391/ADR392/ADR395 are capable of delivering load

currents to 5 mA, with an input voltage that ranges from 2.8 V

(ADR391 only) to 15 V. When these devices are used in

applications with large input voltages, care should be taken to

avoid exceeding the specified maximum power dissipation or

junction temperature because it could result in premature

device failure. The following formula should be used to

calculate the maximum junction temperature or dissipation of

the device:

–

(5)

where:

TJ and TA are, respectively, the junction and ambient temperatures.

PD is the device power dissipation.

θJA is the device package thermal resistance.

SHUTDOWN MODE OPERATION

The ADR391/ADR392/ADR395 include a shutdown feature

that is TTL/CMOS level compatible. A logic low or a zero volt

condition on the SHDN pin is required to turn the devices off.

During shutdown, the output of the reference becomes a high

impedance state, where its potential would then be determined

by external circuitry. If the shutdown feature is not used, the

SHDN pin should be connected to VIN (Pin 2).

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