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ADP151ACBZ-1.2-R7 bảng dữ liệu(PDF) 14 Page - Analog Devices |
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ADP151ACBZ-1.2-R7 bảng dữ liệu(HTML) 14 Page - Analog Devices |
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14 / 24 page ![]() ADP151 Data Sheet Rev. E | Page 14 of 24 Figure 34 through Figure 38 show the typical performance of the 4 V LDO circuit. The noise performance of the 4 V LDO circuit is only about 1 μV worse than the same LDO used at 3.3 V because the output noise of the circuit is almost solely determined by the LDO and not the external components. The small difference may be attributed to the internally generated noise in the LDO ground current working with R2. By keeping R2 small, this noise contribution can be minimized. The PSRR of the 4 V circuit is as much as 10 dB poorer than the 3.3 V LDO with 500 mV of headroom because the ground current of the LDO varies slightly with input voltage. This, in turn, modulates VOFFSET and reduces the PSRR of the regulator. By increasing the headroom to 1 V, the PSRR performance is nearly restored to the performance of the fixed output LDO. 4.04 4.03 4.02 4.01 4.00 3.99 3.98 3.97 3.96 –40 –5 25 85 125 JUNCTION TEMPERATURE (°C) LOAD = 10mA LOAD = 20mA LOAD = 50mA LOAD = 100mA LOAD = 150mA LOAD = 200mA Figure 34. 4 V LDO Circuit, Typical Load Regulation over Temperature VIN (V) LOAD = 10mA LOAD = 20mA LOAD = 50mA LOAD = 100mA LOAD = 150mA LOAD = 200mA 4.040 4.035 4.030 4.025 4.020 4.015 4.010 4.005 4.000 4.4 5.2 5.4 4.8 4.6 5.0 Figure 35. 4 V LDO Circuit, Typical Line Regulation over Load Current 11 10 9 8 1 100 1k 10 LOAD CURRENT (mA) Figure 36. 4 V LDO Circuit, Typical RMS Output Noise, 10 Hz to 100 kHz 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 10 100 1k 10k 100k 1M 10M FREQUENCY (Hz) 200mA 100mA 50mA 10mA Figure 37. 4 V LDO Circuit, Typical PSRR vs. Load Current, 1 V Headroom 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 10 100 1k 10k 100k 1M 10M FREQUENCY (Hz) 200mA 100mA 50mA 10mA Figure 38. 4 V LDO Circuit, Typical PSRR vs. Load Current, 500 mV Headroom |
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