LTC4305CDHD datasheet(13/20 Pages) LINER

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LTC4305

4305f

Figure 4. Protocols Accepted by LTC4305

4305 F04

ACK

0001 100

DEVICE ADDRESS

ACK

START

ACK

10 a4 - a0

XXXXXX r1 r0

ACK

SLAVE

ADDRESS

START

ACK

10 a4 - a0

d7 - d0

DATA

BYTE

STOP

SLAVE

ADDRESS

ACK

START

ACK

10 a4 - a0

XXXXXX r1 r0

ACK

SLAVE

ADDRESS

d7 - d0

DATA

BYTE

STOP

ACK

WRITE BYTE PROTOCOL

READ BYTE PROTOCOL

ALERT RESPONSE ADDRESS PROTOCOL

regardless of their individual address settings. The mass

write can be masked by setting the mass write enable bit

of register 2 to zero. Address (0001 100) is the SMBus

Alert Response Address. Figure 3 shows data transfer

over a 2-wire bus.

Supported Commands

Users must write to the LTC4305 using the SMBus Write

Byte protocol and read from it using the Read Byte

protocol. During fault resolution, the LTC4305 also

supports the Alert Response Address protocol. The

formats for these protocols are shown in Figure 4. Users

must follow the Write Byte protocol exactly to write to the

LTC4305; if a Repeated Start Bit is issued before a Stop

Bit, the LTC4305 ignores the attempted write, and its

control bits remain in their preexisting state. When users

follow the WriteByte protocol exactly, the new data con-

tained in the Data Byte is written into the register selected

by r1 and r0 on the Stop Bit.

OPERATIO

Glitch Filters

The LTC4305 provides glitch filters on the SDAIN and

SCLIN pins as required by the I2C Fast Mode (400kHz)

Specification. The filters prevent signals of up to 50ns

(minimum) time duration and rail-to-rail voltage magni-

tude from passing into the two-wire bus digital interface

circuitry.

Fall Time Control

Per the I2C Fast Mode (400kHz) Specification, the

two-wire bus digital interface circuitry provides fall time

control when forcing logic lows onto the SDAIN bus. The

fall time always meets the limits:

(20 + 0.1

• CB) < tf < 300ns

where tf is the fall time in ns and CB is the equivalent bus

capacitance in pF. Whenever the upstream-downstream

buffer circuitry is active, its output signal will meet the fall

time requirements, provided that its input signal meets the

fall time requirements.

Figure 3. Data Transfer Over I2C/SMBus

SCL

SDA

START

CONDITION

STOP

CONDITION

ADDRESS

R/W

ACK

DATA

ACK

DATA

ACK

1 - 7

4305 F03

a6 - a0

d7 - d0

1 - 7

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