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BQ76PL536APAPR bảng dữ liệu(PDF) 13 Page - Texas Instruments

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tên linh kiện BQ76PL536APAPR
Giải thích chi tiết về linh kiện  3 to 6 Series Cell Lithium-Ion Battery Monitor and Secondary Protection IC for Applications
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BQ76PL536APAPR bảng dữ liệu(HTML) 13 Page - Texas Instruments

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t CS,LEAD
CS
t CS,LAG
t(SCLK )
SCLK
t(HIGH)
t(LOW)
SDI
tSU,SDI
tHD,SDI
SDO
tACC
tVALID, SDO
tDIS
t CS _ DLY
bq76PL536A
www.ti.com
SLUSAD3A – JUNE 2011 – REVISED AUGUST 2012
AC TIMING CHARACTERISTICS
SPI DATA INTERFACE
Typical values stated where TA = 25°C and VBAT = 20 V, Min/Max values stated where TA = –40˚C to 85°C and VBAT = 7.2 V
to 27 V (unless otherwise noted)
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
fSCLK
SCLK frequency(1)
10
250
1000
kHz
SCLKDC
SCLK_H duty cycle, t(HIGH) / t(SCLK) or t(LOW) / t(SCLK)
40%
60%
tCS,LEAD
CS_H lead time, CS_H low to clock
50
SCLK/2
ns
tCS,LAG
CS_H lag time. Last clock to CS_H high
10
SCLK/2
ns
tCS,DLY
CS_H high to CS_H low (inter-packet delay requirement)
3
µs
tACC
CS_H access time(2): CS_H low to SDO_H data out
125
250
ns
CS_H disable time(2): CS_H high to SDO_H high
tDIS
2.5
2.7
µs
impedance
tSU,SDI
SDI_H input-data setup time
15
ns
tHD,SDI
SDI_H input-data hold time
10
ns
SDO_H output-data valid time
tVALID,SDO
CL ≤ 20 pF
75
110
ns
SCLK_H edge to SDO_H valid
(1)
Maximum SCLK frequency is limited by the number of bq76PL536A devices in the vertical stack. The maximum listed here may not be
realizable in systems due to delays and limits imposed by other components including wiring, connectors, PCB material and routing, etc.
See text for details.
(2)
Time listed is for single device.
Figure 3. SPI Host Interface Timing
Copyright © 2011–2012, Texas Instruments Incorporated
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