ADM1066ASUZ datasheet(7/32 Pages) AD

7 / 32 page

ADM1066

Rev. E | Page 7 of 32

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

DIGITAL INPUTS (VXx, A0, A1)

Input High Voltage, VIH

2.0

Maximum VIN = 5.5 V

Input Low Voltage, VIL

0.8

Maximum VIN = 5.5 V

Input High Current, IIH

−1

μA

VIN = 5.5 V

Input Low Current, IIL

μA

VIN = 0 V

Input Capacitance

Programmable Pull-Down

Current, IPULL-DOWN

μA

VDDCAP = 4.75 V, TA = 25°C, if known logic state is required

SERIAL BUS DIGITAL INPUTS

(SDA, SCL)

Input High Voltage, VIH

2.0

Input Low Voltage, VIL

0.8

Output Low Voltage, VOL2

0.4

IOUT = −3.0 mA

SERIAL BUS TIMING3

Clock Frequency, fSCLK

400

kHz

Bus Free Time, tBUF

1.3

μs

Start Setup Time, tSU;STA

0.6

μs

Stop Setup Time, tSU;STO

0.6

μs

Start Hold Time, tHD;STA

0.6

μs

SCL Low Time, tLOW

1.3

μs

SCL High Time, tHIGH

0.6

μs

SCL, SDA Rise Time, tR

300

SCL, SDA Fall Time, tF

300

Data Setup Time, tSU;DAT

100

Data Hold Time, tHD;DAT

Input Low Current, IIL

μA

VIN = 0 V

SEQUENCING ENGINE TIMING

State Change Time

μs

1 At least one of the VH, VPx pins must be ≥3.0 V to maintain the device supply on VDDCAP.

2 Specification is not production tested but is supported by characterization data at initial product release.

3 Timing specifications are guaranteed by design and supported by characterization data.

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