REV. A

AD9848/AD9849

–22–

UP TO FOUR INDIVIDUAL HORIZONTAL CLAMP AND BLANKING REGIONS MAY BE

PROGRAMMED WITHIN A SINGLE FIELD, USING THE SEQUENCE CHANGE POSITIONS.

SEQUENCE CHANGE OF POSITION #1

SEQUENCE CHANGE OF POSITION #2

SEQUENCE CHANGE OF POSITION #3

SINGLE FIELD (1 VD INTERVAL)

CLAMP AND PBLK SEQUENCE REGION 0

SEQUENCE CHANGE OF POSITION #0

(V-COUNTER = 0)

CLAMP AND PBLK SEQUENCE REGION 3

CLAMP AND PBLK SEQUENCE REGION 2

CLAMP AND PBLK SEQUENCE REGION 1

Figure 12. Clamp and Blanking Sequence Flexibility

Table IV. CLPOB, CLPDM, PBLK Individual Sequence Parameters

Register Name

Length

Range

Description

SPOL

1b

High/Low

Starting Polarity of Clamp and Blanking Pulses for Sequences 0–3

TOG1

12b

0–4095 Pixel Location

First Toggle Position within the Line for Sequences 0–3

TOG2

12b

0–4095 Pixel Location

Second Toggle Position within the Line for Sequences 0–3

Table V. HBLK Individual Sequence Parameters

Register Name

Length

Range

Description

HBLKMASK

1b

High/Low

Masking Polarity for H1 for Sequences 0–3 (0 = H1 Low, 1 = H1 High)

HBLKTOG1

12b

0–4095 Pixel Location

First Toggle Position within the Line for Sequences 0–3

HBLKTOG2

12b

0–4095 Pixel Location

Second Toggle Position within the Line for Sequences 0–3

Table VI. Horizontal Sequence Control Parameters for CLPOB, CLPDM, PBLK, and HBLK

Register Name

Length

Range

Description

SCP1–SCP3

12b

0–4095 Line Number

CLAMP/BLANK SCP to Define Horizontal Regions 0–3

SPTR0–SPTR3

2b

0–3 Sequence Number

Sequence Pointer for Horizontal Regions 0–3

H-Counter Synchronization

The H-Counter reset occurs on the sixth CLI rising edge following the HD falling edge. The PxGA steering is synchronized with the

reset of the internal H-Counter (see Figure 13).

000

1

12

111

0

03

11

00

01234

5

6

7

89

10

11

12

14

15

01

2

3

02

3

4

H-COUNTER

RESET

VD

NOTES

1. INTERNAL H-COUNTER IS RESET ON THE SIXTH CLI RISING EDGE FOLLOWING THE HD FALLING EDGE.

2. PxGA STEERING IS SYNCRONIZED WITH THE RESET OF THE INTERNAL H-COUNTER (MOSAIC SEPARATE MODE IS SHOWN).

3. VD FALLING EDGE SHOULD OCCUR ONE CLOCK CYCLE BEFORE HD FALLING EDGE FOR PROPER PxGA LINE SYNCHRONIZATION.

HD

XX

XX

X

X

X

PxGA GAIN

REGISTER

CLI

XX

XX

X

X

X

H-COUNTER

(PIXEL COUNTER)

3ns MIN

23

5

3ns MIN

X

X

Figure 13. H-Counter Synchronization