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AD9786BSVRL bảng dữ liệu(PDF) 10 Page - Analog Devices

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Trang chủ  http://www.analog.com
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AD9786BSVRL bảng dữ liệu(HTML) 10 Page - Analog Devices

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AD9786
Rev. B | Page 10 of 56
ANALOG
Table 7. Analog Pin Function Descriptions
Pin No.
Mnemonic
Direction
Description
59
REFIO
A
Reference.
60
FSADJ
A
Full-Scale Adjust.
70, 71
IOUTB, IOUTA
A
Differential DAC Output Currents.
61
DNC
Do Not Connect.
62, 79
ADVDD
Analog Domain Digital Content 2.5 V.
63, 78
ADGND
Analog Domain Digital Content 0 V.
64, 77
ACVDD
Analog Domain Clock Content 2.5 V.
65, 76
ACGND
Analog Domain Clock Content 0 V.
66, 75
AVDD2
Analog Domain Clock Switching 3.3 V.
67, 74
AGND2
Analog Domain Switching 0 V.
68, 73
AVDD1
Analog Domain Quiet 3.3 V.
69, 72
AGND1
Analog Domain Quiet 0 V.
80
DNC
Do Not Connect.
DATA
Table 8. Data Pin Function Descriptions
Pin No.
Mnemonic
Direction
Description
Input Data Port 1.
ONEPORT
0x02[6]
Mode
0
Latched data routed for I channel processing.
10 to 15, 18 to
24, 27 to 29
P1B15 to P1B0
I
1
Latched data demultiplexed by IQSEL and routed for
interleaved I/Q processing.
ONEPORT
0x02[6]
IQPOL
0x02[1]
IQSEL/
P2B15
Mode (IQPOL = 0)
0
X
X
Latched data routed to Q channel Bit 15
(MSB) processing.
1
0
0
Latched data on Data Port 1 routed to Q
channel processing.
1
0
1
Latched data on Data Port 1 routed to I
channel processing.
1
1
0
Latched data on Data Port 1 routed to I
channel processing.
32
IQSEL/P2B15
I
1
1
1
Latched data on Data Port 1 routed to Q
channel processing.
ONEPORT
0x02[6]
0
Latched data routed for Q channel Bit 14 processing.
33
ONEPORTCLOCK/P2B14
I/O
1
Pin configured for output of clock at twice the channel
data route.
34, 37 to 43,
46 to 51
P2B13 to P2B0
I
Input Data Port 2, Bit 13 to Bit 0.
30
DRVDD
Digital Output Pin Supply, 3.3 V.
9, 17, 26,
36, 44, 52
DVDD
Digital Domain, 2.5 V.
8, 16, 25,
35, 45, 53
DGND
Digital Domain, 0 V.



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