AD9773BSVZRL datasheet(49/60 Pages) AD

49 / 60 page

AD9773

Rev. D | Page 49 of 60

SIGNAL GENERATOR

CLK+/CLK–

DATACLK

LECROY

PULSE

GENERATOR

TRIG

INP

AWG2021

DG2020

INPUT CLOCK

DAC1, DB11–DB0

AD9773

DAC2, DB11–DB0

40-PIN RIBBON CABLE

JUMPER CONFIGURATION FOR TWO-PORT MODE, PLL ON

JP1 –

JP2 –

JP3 –

JP5 –

JP6 –

JP12 –

JP24 –

JP25 –

JP26 –

JP27 –

JP31 –

JP32 –

JP33 –

SOLDERED/IN

UNSOLDERED/OUT

NOTES

1. TO USE PECL DRIVER (U8), SOLDER JP41 AND JP42 AND REMOVE TRANSFORMER T1.

2. IN TWO-PORT MODE, IF DATACLK/PLL_LOCK IS PROGRAMMED TO OUTPUT PIN 8, JP25

AND JP39 SHOULD BE SOLDERED. IF DATACLK/PLL_LOCK IS PROGRAMMED TO OUTPUT

PIN 53, JP46 AND JP47 SHOULD BE SOLDERED. FOR MORE INFORMATION, SEE THE

TWO-PORT DATA INPUT MODE SECTION.

Figure 101. Test Configuration for AD9773 in Two-Port Mode with PLL Enabled, Signal Generator Frequency = Input Data Rate,

DAC Output Data Rate = Signal Generator Frequency × Interpolation Rate

SIGNAL GENERATOR

CLK+/CLK–

ONEPORTCLK

LECROY

PULSE

GENERATOR

TRIG

INP

AWG2021

DG2020

INPUT CLOCK

DAC1, DB11–DB0

AD9773

DAC2, DB11–DB0

JUMPER CONFIGURATION FOR ONE-PORT MODE, PLL ON

JP1 –

JP2 –

JP3 –

JP5 –

JP6 –

JP12 –

JP24 –

JP25 –

JP26 –

JP27 –

JP31 –

JP32 –

JP33 –

SOLDERED/IN

UNSOLDERED/OUT

NOTES

1. TO USE PECL DRIVER (U8), SOLDER JP41 AND JP42 AND REMOVE TRANSFORMER T1.

Figure 102. Test Configuration for AD9773 in One-Port Mode with PLL Enabled, Signal Generator Frequency = One-Half Interleaved Input Data Rate,

ONEPORTCLK = Interleaved Input Data Rate, DAC Output Data Rate = Signal Generator Frequency × Interpolation Rate

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