LPC4370 datasheet(80/150 Pages) NXP

80 / 150 page

LPC4370

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Product data sheet

Rev. 2 — 21 October 2013

80 of 150

NXP Semiconductors

LPC4370

32-bit ARM Cortex-M4/M0 microcontroller

digital and analog function, the ADC function select registers in the SCU enable the

analog function.

A separate set of analog I/Os for the ADCs and the DAC as well as most USB pins are

located on separate pads and are not controlled through the SCU.

In addition, the clock delay register for the SDRAM EMC_CLK pins and the registers that

select the pin interrupts are located in the SCU.

7.23.3 Clock Generation Unit (CGU)

The Clock Generator Unit (CGU) generates several base clocks. The CGU outputs are

unrelated in frequency and phase and can have different clock sources within the CGU.

One CGU output is routed to the CLKOUT pins.

Within each clock area there may be multiple branch clocks, which offers very flexible

control for power-management purposes. All branch clocks are outputs of one of two

Clock Control Units (CCUs) and can be controlled independently. Branch clocks derived

from the same base clock are synchronous in frequency and phase.

7.23.4 Internal RC oscillator (IRC)

The IRC is used as the clock source for the WWDT and/or as the clock that drives the

PLLs and subsequently the CPU. The nominal IRC frequency is 12 MHz. The IRC is

trimmed to 1 % accuracy over the entire voltage and temperature range.

Upon power-up or any chip reset, the LPC4370 use the IRC as the clock source. Software

may later switch to one of the other available clock sources.

7.23.5 PLL0USB (for USB0)

PLL0 is a dedicated PLL for the USB0 High-speed controller.

PLL0 accepts an input clock frequency from an external oscillator in the range of 14 kHz

to 25 MHz. The input frequency is multiplied up to a high frequency with a Current

Controlled Oscillator (CCO). The CCO operates in the range of 4.3 MHz to 550 MHz.

7.23.6 PLL0AUDIO (for audio)

The audio PLL PLL0AUDIO is a general purpose PLL with a very small step size. This

PLL accepts an input clock frequency derived from an external oscillator or internal IRC.

The input frequency is multiplied up to a high frequency with a Current Controlled

Oscillator (CCO). A sigma-delta converter modulates the PLL divider ratios to obtain the

desired output frequency. The output frequency can be set as a multiple of the sampling

frequency fs to 32fs, 64fs, 128  fs, 256  fs, 384  fs, 512  fs and the sampling

frequency fs can range from 16 kHz to 192 kHz (16, 22.05, 32, 44.1, 48, 96,192) kHz.

Many other frequencies are possible as well.

7.23.7 System PLL1

The PLL1 accepts an input clock frequency from an external oscillator in the range of

10 MHz to 25 MHz. The input frequency is multiplied up to a high frequency with a Current

Controlled Oscillator (CCO). The multiplier can be an integer value from 1 to 32. The CCO

operates in the range of 156 MHz to 320 MHz, so there is an additional divider in the loop

to keep the CCO within its frequency range while the PLL is providing the desired output

frequency. The output divider may be set to divide by 2, 4, 8, or 16 to produce the output

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