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CDC351DBLE bảng dữ liệu(PDF) 5 Page - Texas Instruments

tên linh kiện CDC351DBLE
Giải thích chi tiết về linh kiện  1-LINE TO 10-LINE CLOCK DRIVER WITH 3-STATE OUTPUTS
PDF  13 Pages
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Trang chủ  http://www.ti.com
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CDC351DBLE bảng dữ liệu(HTML) 5 Page - Texas Instruments

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From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1
6 V
Open
GND
500
Ω
500
Ω
TEST
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
S1
Open
6 V
GND
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 6 V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
1.5 V
1.5 V
3 V
0 V
1.5 V
VOL + 0.3 V
1.5 V
VOH - 0.3 V
≈ 0 V
3 V
Data Input
Timing Input
1.5 V
3 V
0 V
1.5 V
1.5 V
3 V
0 V
3 V
0 V
1.5 V
1.5 V
tw
Input
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
tPLH
tPHL
Output
1.5 V
1.5 V
3 V
0 V
1.5 V
VOH
VOL
Input
0.8 V
2 V
tr
tf
0.8 V
2 V
CDC351. CDC351I
1-LINE TO 10-LINE CLOCK DRIVER WITH 3-STATE OUTPUTS
SCAS441D – FEBRUARY 1994 – REVISED OCTOBER 2003
A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output
control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the
output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
≤ 10 MHz, Z
O = 50 Ω, tr≤ 2.5 ns,
tf≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
5



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