IN1

MUX

GND

SAMPLING

CAPACITOR

SW1

-

+

CONTROL

LOGIC

CHARGE

REDISTRIBUTION

DAC

SW2

IN2

2

IN1

MUX

GND

SAMPLING

CAPACITOR

SW1

-

+

CONTROL

LOGIC

CHARGE

REDISTRIBUTION

DAC

SW2

IN2

2

ADC102S021

SNAS281G – FEBRUARY 2005 – REVISED MARCH 2013

www.ti.com

APPLICATIONS INFORMATION

ADC102S021 OPERATION

The ADC102S021 is a successive-approximation analog-to-digital converter designed around a charge-

redistribution digital-to-analog converter. Simplified schematics of the ADC102S021 in both track and hold modes

are shown in Figure 47 and Figure 48, respectively. In Figure 47, the ADC102S021 is in track mode: switch SW1

connects the sampling capacitor to one of two analog input channels through the multiplexer, and SW2 balances

the comparator inputs. The ADC102S021 is in this state for the first three SCLK cycles after CS is brought low.

Figure 48 shows the ADC102S021 in hold mode: switch SW1 connects the sampling capacitor to ground,

maintaining the sampled voltage, and switch SW2 unbalances the comparator. The control logic then instructs

the charge-redistribution DAC to add fixed amounts of charge to the sampling capacitor until the comparator is

balanced. When the comparator is balanced, the digital word supplied to the DAC is the digital representation of

the analog input voltage. The ADC102S021 is in this state for the fourth through sixteenth SCLK cycles after CS

is brought low.

The time when CS is low is considered a serial frame. Each of these frames should contain an integer multiple of

16 SCLK cycles, during which time a conversion is performed and clocked out at the DOUT pin and data is

clocked into the DIN pin to indicate the multiplexer address for the next conversion.

Figure 47. ADC102S021 in Track Mode

Figure 48. ADC102S021 in Hold Mode

USING THE ADC102S021

An ADC102S021 timing diagram and a serial interface timing diagram for the ADC102S021 are shown in the

Timing Diagrams section. CS is chip select, which initiates conversions and frames the serial data transfers.

SCLK (serial clock) controls both the conversion process and the timing of serial data. DOUT is the serial data

output pin, where a conversion result is sent as a serial data stream, MSB first. Data to be written to the

ADC102S021's Control Register is placed at DIN, the serial data input pin. New data is written to DIN with each

conversion.

A serial frame is initiated on the falling edge of CS and ends on the rising edge of CS. Each frame must contain

an integer multiple of 16 rising SCLK edges. The ADC output data (DOUT) is in a high impedance state when

CS is high and is active when CS is low. Thus, CS acts as an output enable. Additionally, the device goes into a

power down state when CS is high and also between continuous conversion cycles.

16

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