AD9517-1ASLASHPCBZ datasheet(62/80 Pages) AD

62 / 80 page

AD9517-1

Data Sheet

Rev. E | Page 62 of 80

Reg.

Addr.

(Hex)

Bits

Name

Description

0x017

[1:0]

Antibacklash

Antibacklash Pulse Width (ns)

pulse width

2.9 (default). This is the recommended setting; it does not normally need to be changed.

1.3. This setting may be necessary if the PFD frequency > 50 MHz.

6.0.

2.9.

0x018

[6:5]

Lock detect

counter

Required consecutive number of PFD cycles with edges inside lock detect window before the DLD indicates a locked

condition.

PFD Cycles to Determine Lock

5 (default).

16.

64.

255.

Digital lock detect

window

If the time difference of the rising edges at the inputs to the PFD is less than the lock detect window time, the digital lock

detect flag is set. The flag remains set until the time difference is greater than the loss-of-lock threshold.

0: high range (default).

1: low range.

Disable digital

Digital lock detect operation.

lock detect

0: normal lock detect operation (default).

1: disables lock detect.

[2:1]

VCO cal divider

VCO calibration divider. Divider used to generate the VCO calibration clock from the PLL reference clock.

VCO Calibration Clock Divider

2. This setting is fine for PFD frequencies < 12.5 MHz. The PFD frequency is fREF/R.

4. This setting is fine for PFD frequencies < 25 MHz.

8. This setting is fine for PFD frequencies < 50 MHz.

16 (default). This setting is fine for any PFD frequency but also results in the longest VCO calibration time.

VCO cal now

Bit used to initiate the VCO calibration. This bit must be toggled from 0b to 1b in the active registers. To initiate

calibration, use the following three steps: first, ensure that the input reference signal is present; second, set to 0b

(if not zero already), followed by an update bit (Register 0x232, Bit 0); and third, program to 1b, followed by another

update bit (Register 0x232, Bit 0). Clearing this bit discards the VCO calibration and usually results in the PLL losing lock.

The user must ensure that the holdover enable bits in Register 0x01D = 00b during VCO calibration.

0x019

[7:6]

R, A, B counters

Action

SYNC pin reset

Does nothing on SYNC (default).

Asynchronous reset.

Synchronous reset.

Does nothing on SYNC.

[5:3]

R path delay

R path delay (default = 0x00) (see

Table 2).

[2:0]

N path delay

N path delay (default = 0x00) (see

Table 2).

AD9517-1A/PCBZ bảng dữ liệu(PDF) 62 Page - Analog Devices

AD9517-1A/PCBZ bảng dữ liệu(HTML) 62 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80

bảng dữ liệu tải về

Link URL