AD7477AARMZ datasheet(21/28 Pages) AD

21 / 28 page

AD7476A/AD7477A/AD7478A

Rev. F | Page 21 of 28

SERIAL INTERFACE

Figure 24, Figure 25, and Figure 26 show the detailed timing

diagrams for serial interfacing to the AD7476A, AD7477A, and

AD7478A, respectively. The serial clock provides the conversion

clock and also controls the transfer of information from the

AD7476A/AD7477A/AD7478A during conversion.

The CS signal initiates the data transfer and conversion process.

The falling edge of CS puts the track-and-hold into hold mode

and takes the bus out of three-state; the analog input is sampled

at this point. Also, the conversion is initiated at this point.

For the AD7476A, the conversion requires 16 SCLK cycles to

complete. Once 13 SCLK falling edges have elapsed, the track-

and-hold goes back into track on the next SCLK rising edge, as

shown in Figure 24 at Point B. On the 16th SCLK falling edge,

the SDATA line goes back into three-state. If the rising edge of

CS occurs before 16 SCLKs have elapsed, the conversion is

terminated and the SDATA line goes back into three-state;

otherwise, SDATA returns to three-state on the 16th SCLK

falling edge, as shown in Figure 24. Sixteen serial clock cycles

are required to perform the conversion process and to access

data from the AD7476A.

For the AD7477A, the conversion requires 14 SCLK cycles to

complete. Once 13 SCLK falling edges have elapsed, the track-

and-hold goes back into track on the next rising edge as shown

at Point B in Figure 25. If the rising edge of CS occurs before

14 SCLKs have elapsed, the conversion is terminated and the

SDATA line goes back into three-state. If 16 SCLKs are

considered in the cycle, SDATA returns to three-state on the

16th SCLK falling edge, as shown in Figure 25.

For the AD7478A, the conversion requires 12 SCLK cycles to

complete. The track-and-hold goes back into track on the rising

edge after the 11th falling edge, as shown in Figure 26 at Point B. If

the rising edge of CS occurs before 12 SCLKs have elapsed, the

conversion is terminated and the SDATA line goes back into three-

state. If 16 SCLKs are considered in the cycle, SDATA returns to

three-state on the 16th SCLK falling edge, as shown in Figure 26.

SCLK

SDATA

tCONVERT

tQUIET

ZERO

DB11

DB10

DB2

DB1

DB0

THREE-STATE

THREE-

STATE

4 LEADING ZEROS

1/THROUGHPUT

Figure 24. AD7476A Serial Interface Timing Diagram

SCLK

THREE-STATE

DB9

DB8

DB0

ZERO

4 LEADING ZEROS

ZERO

1/ THROUGHPUT

ZERO

2 TRAILING ZEROS

SDATA

tCONVERT

tQUIET

THREE-STATE

Figure 25. AD7477A Serial Interface Timing Diagram

SCLK

SDATA

4 LEADING ZEROS

THREE-STATE

DB7

ZERO

1/ THROUGHPUT

ZERO

4 TRAILING ZEROS

tCONVERT

tQUIET

Figure 26. AD7478A Serial Interface Timing Diagram

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