PIC18F2610ESLASHSOSQTP datasheet(253/376 Pages) MICROCHIP

253 / 376 page

DS39636D-page 255

PIC18F2X1X/4X1X

22.5.1

PROGRAM MEMORY

CODE PROTECTION

The program memory may be read to or written from

any location using the table read and table write

instructions. The Device ID may be read with table

reads. The Configuration registers may be read and

written with the table read and table write instructions.

In Normal Execution mode, the CPn bits have no direct

effect. CPn bits inhibit external reads and writes. The

EBTRn bits control table reads. For a block of user

memory with the EBTRn bit set to ‘0’, a table read

instruction that executes from within that block is

allowed to read. A table read instruction that executes

from a location outside of that block is not allowed to

read and will result in reading ‘0’s. Figures 22-7

through 22-10 illustrate table write and table read

protection.

FIGURE 22-7:

EXTERNAL BLOCK TABLE READ (EBTRn) DISALLOWED

(16-KBYTE AND 32-KBYTE DEVICES)

Note:

Code protection bits may only be written to

a ‘0’ from a ‘1’ state. It is not possible to

write a ‘1’ to a bit in the ‘0’ state. Code

protection bits are only set to ‘1’ by a full

chip erase or block erase function. The full

chip erase and block erase functions can

only be initiated via ICSP or an external

programmer.

WRTB, EBTRB = 11

WRT0, EBTR0 = 10

WRT1, EBTR1 = 11

WRT2, EBTR2 = 11

WRT3, EBTR3 = 11

TBLRD*

TBLPTR = 0008FFh

PC = 003FFEh

Results: All table reads from external blocks to Blockn are disabled whenever EBTRn = 0.

TABLAT register returns a value of ‘0’.

Program Memory

Configuration Bit Settings

000000h

0007FFh

000800h

001FFFh

002000h

003FFFh

004000h

005FFFh

006000h

007FFFh

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