PIC18F1220ESLASHSSSQTP datasheet(148/308 Pages) MICROCHIP

148 / 308 page

PIC18F1220/1320

DS39605F-page 146

16.3.5

BREAK CHARACTER SEQUENCE

The Enhanced USART module has the capability of

sending the special Break character sequences that

are required by the LIN bus standard. The Break char-

acter transmit consists of a Start bit, followed by twelve

‘0’ bits and a Stop bit. The Frame Break character is

sent whenever the SENDB and TXEN bits (TXSTA<3>

and TXSTA<5>) are set while the Transmit Shift

written to TXREG will be ignored and all ‘0’s will be

transmitted.

The SENDB bit is automatically reset by hardware after

the corresponding Stop bit is sent. This allows the user

to preload the transmit FIFO with the next transmit byte

following the Break character (typically, the Sync

character in the LIN specification).

Note that the data value written to the TXREG for the

Break character is ignored. The write simply serves the

purpose of initiating the proper sequence.

The TRMT bit indicates when the transmit operation is

active or Idle, just as it does during normal transmis-

sion. See Figure 16-9 for the timing of the Break

character sequence.

16.3.5.1

Transmitting A Break Signal

The Enhanced USART module has the capability of

sending the Break signal that is required by the LIN bus

standard. The Break signal consists of a Start bit,

followed by twelve ‘0’ bits and a Stop bit. The Break sig-

nal is sent whenever the SENDB (TXSTA<3>) and

TXEN (TXSTA<5>) bits are set and TXREG is loaded

with data. The data written to TXREG will be ignored

and all ‘0’s will be transmitted.

SENDB is automatically cleared by hardware when the

Break signal has been sent. This allows the user to

preload the transmit FIFO with the next transmit byte

following the Break character (typically, the Sync

character in the LIN specification).

The TRMT bit indicates when the transmit operation is

active

Idle,

just

does

during

normal

transmission.

To send a Break Signal:

Configure the EUSART for asynchronous trans-

missions (steps 1-5). Initialize the SPBRG register

for the appropriate baud rate. If a high-speed baud

rate is desired, set bit BRGH (see Section 16.2

“EUSART Baud Rate Generator (BRG)”).

Enable the asynchronous serial port by clearing

bit SYNC and setting bit SPEN.

If interrupts are desired, set enable bit TXIE.

If 9-bit transmission is desired, set transmit bit

TX9. Can be used as address/data bit.

Enable the transmission by setting bit TXEN,

which will also set bit TXIF.

Set the SENDB bit.

Load a byte into TXREG. This triggers sending a

Break signal. The Break signal is complete

when TRMT is set. SENDB will also be cleared.

See Figure 16-9 for the timing of the Break signal

sequence.

16.3.6

RECEIVING A BREAK CHARACTER

The Enhanced USART module can receive a Break

character in two ways.

The first method forces configuration of the baud rate

at a frequency of 9/13 the typical speed. This allows for

the Stop bit transition to be at the correct sampling

location (12 bits for Break versus Start bit and 8 data

bits for typical data).

The second method uses the auto-wake-up feature

described in Section 16.3.4 “Auto-Wake-up on Sync

Break Character”. By enabling this feature, the

EUSART will sample the next two transitions on RX/DT,

cause an RCIF interrupt and receive the next data byte

followed by another interrupt.

Note that following a Break character, the user will

typically want to enable the Auto-Baud Rate Detect

feature. For both methods, the user can set the ABD bit

before placing the EUSART in its Sleep mode.

16.3.6.1

Transmitting a Break Sync

The following sequence will send a message frame

header made up of a Break, followed by an auto-baud

Sync byte. This sequence is typical of a LIN bus master.

Configure the EUSART for the desired mode.

Set the TXEN and SENDB bits to set up the

Break character.

Load the TXREG with a dummy character to

initiate transmission (the value is ignored).

Write ‘55h’ to TXREG to load the Sync character

into the transmit FIFO buffer.

After the Break has been sent, the SENDB bit is

reset by hardware. The Sync character now

transmits in the preconfigured mode. When the

TXREG becomes empty, as indicated by the

TXIF, the next data byte can be written to TXREG.

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