PIC18F1220ESLASHSSSQTP datasheet(10/308 Pages) MICROCHIP

10 / 308 page

PIC18F1220/1320

DS39605F-page 8

TABLE 1-2:

PIC18F1220/1320 PINOUT I/O DESCRIPTIONS

Pin Name

Pin Number

Type

Buffer

Type

Description

PDIP/

SOIC

SSOP

QFN

MCLR/VPP/RA5

MCLR

VPP

RA5

—

Master Clear (input) or programming voltage (input).

Master Clear (Reset) input. This pin is an active-low

Reset to the device.

Programming voltage input.

Digital input.

OSC1/CLKI/RA7

OSC1

CLKI

RA7

I/O

CMOS

Oscillator crystal or external clock input.

Oscillator crystal input or external clock source

input. ST buffer when configured in RC mode,

CMOS otherwise.

External clock source input. Always associated with

pin function OSC1. (See related OSC1/CLKI,

OSC2/CLKO pins.)

General purpose I/O pin.

OSC2/CLKO/RA6

OSC2

CLKO

RA6

I/O

—

Oscillator crystal or clock output.

Oscillator crystal output. Connects to crystal or

resonator in Crystal Oscillator mode.

In RC, EC and INTRC modes, OSC2 pin outputs

CLKO, which has 1/4 the frequency of OSC1 and

denotes instruction cycle rate.

General purpose I/O pin.

PORTA is a bidirectional I/O port.

RA0/AN0

RA0

AN0

I/O

Analog

Digital I/O.

Analog input 0.

RA1/AN1/LVDIN

RA1

AN1

LVDIN

I/O

Analog

Digital I/O.

Analog input 1.

Low-Voltage Detect input.

RA2/AN2/VREF-

RA2

AN2

VREF-

I/O

Analog

Digital I/O.

Analog input 2.

A/D reference voltage (low) input.

RA3/AN3/VREF+

RA3

AN3

VREF+

I/O

Analog

Digital I/O.

Analog input 3.

A/D reference voltage (high) input.

RA4/T0CKI

RA4

T0CKI

I/O

ST/OD

Digital I/O. Open-drain when configured as output.

Timer0 external clock input.

RA5

See the MCLR/VPP/RA5 pin.

RA6

See the OSC2/CLKO/RA6 pin.

RA7

See the OSC1/CLKI/RA7 pin.

Legend:

TTL =

TTL compatible input

CMOS = CMOS compatible input or output

Schmitt Trigger input with CMOS levels

= Input

Output

= Power

Open-drain (no P diode to VDD)

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