PIC18F1220ESLASHSSSQTP datasheet(267/308 Pages) MICROCHIP

267 / 308 page

DS39605F-page 265

PIC18F1220/1320

FIGURE 22-14:

A/D CONVERSION TIMING

TABLE 22-14: A/D CONVERSION REQUIREMENTS

131

130

132

BSF ADCON0, GO

A/D CLK(1)

A/D DATA

ADRES

ADIF

SAMPLE

OLD_DATA

Sampling Stopped

DONE

NEW_DATA

(Note 2)

Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts.

This allows the SLEEP instruction to be executed.

2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.

. . .

TCY

Param

No.

Symbol

Characteristic

Min

Max

Units

Conditions

130

TAD

A/D Clock Period

PIC18F1X20

1.6

20(5)

μsTOSC based, VREF ≥ 3.0V

PIC18LF1X20

3.0

20(5)

μsTOSC based, VREF full range

PIC18F1X20

2.0

6.0

μs

A/D RC mode

PIC18LF1X20

3.0

9.0

μs

A/D RC mode

131

TCNV

Conversion Time

(not including acquisition time) (Note 1)

TAD

132

TACQ

Acquisition Time (Note 3)

—

μs

-40

°C ≤ Temp ≤ +125°C

135

TSWC

Switching Time from Convert

→ Sample

—

(Note 4)

136

TAMP

Amplifier Settling Time (Note 2)

1—

μs

This may be used if the

“new” input voltage has not

changed by more than 1 LSb

(i.e., 5 mV @ 5.12V) from the

last sampled voltage (as

stated on CHOLD).

Note 1:

ADRES register may be read on the following TCY cycle.

See Section 17.0 “10-Bit Analog-to-Digital Converter (A/D) Module” for minimum conditions when input

voltage has changed more than 1 LSb.

The time for the holding capacitor to acquire the “New” input voltage, when the voltage changes full scale after

the conversion (AVDD to AVSS, or AVSS to AVDD). The source impedance (RS) on the input channels is 50

Ω.

On the next Q4 cycle of the device clock.

The time of the A/D clock period is dependent on the device frequency and the TAD clock divider.

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