PIC18F1220ESLASHSOSQTP datasheet(182/308 Pages) MICROCHIP

182 / 308 page

PIC18F1220/1320

DS39605F-page 180

19.2

Watchdog Timer (WDT)

For PIC18F1220/1320 devices, the WDT is driven by the

INTRC source. When the WDT is enabled, the clock

source is also enabled. The nominal WDT period is 4 ms

and has the same stability as the INTRC oscillator.

The 4 ms period of the WDT is multiplied by a 16-bit

postscaler. Any output of the WDT postscaler is selected

by a multiplexer, controlled by bits in Configuration

131.072 seconds (2.18 minutes). The WDT and

postscaler are cleared when any of the following events

occur: execute a SLEEP or CLRWDT instruction, the IRCF

bits (OSCCON<6:4>) are changed or a clock failure has

occurred.

Adjustments to the internal oscillator clock period using

the OSCTUNE register also affect the period of the

WDT by the same factor. For example, if the INTRC

period is increased by 3%, then the WDT period is

increased by 3%.

19.2.1

CONTROL REGISTER

readable and writable register, which contains a control

bit that allows software to override the WDT enable

configuration bit, only if the configuration bit has

disabled the WDT.

FIGURE 19-1:

WDT BLOCK DIAGRAM

Note 1: The CLRWDT and SLEEP instructions

clear the WDT and postscaler counts

when executed.

2: Changing the setting of the IRCF bits

(OSCCON<6:4>) clears the WDT and

postscaler counts.

3: When a CLRWDT instruction is executed

the postscaler count will be cleared.

U-0

R/W-0

—

—SWDTEN

bit 7

bit 0

bit 7-1

Unimplemented: Read as ‘0’

bit 0

SWDTEN: Software Controlled Watchdog Timer Enable bit

= Watchdog Timer is on

= Watchdog Timer is off

Note:

This bit has no effect if the configuration bit, WDTEN (CONFIG2H<0>), is enabled.

Legend:

R = Readable bit

W = Writable bit

-n = Value at POR

U = Unimplemented bit, read as ‘0’

INTRC Oscillator

WDT

Wake-up

Reset

WDT

WDT Counter

(31 kHz)

Programmable Postscaler

1:1 to 1:32,768

Enable WDT

WDTPS<3:0>

SWDTEN

WDTEN

CLRWDT

from Sleep

Reset

All Device

Sleep

INTRC Control

Resets

÷125

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