PIC18F1220ESLASHSOSQTP datasheet(25/308 Pages) MICROCHIP

25 / 308 page

DS39605F-page 23

PIC18F1220/1320

3.3.1

PRI_IDLE MODE

This mode is unique among the three Low-Power Idle

modes, in that it does not disable the primary system

clock. For timing sensitive applications, this allows for

the fastest resumption of device operation with its more

accurate primary clock source, since the clock source

does not have to “warm up” or transition from another

oscillator.

PRI_IDLE mode is entered by setting the IDLEN bit,

clearing the SCS bits and executing a SLEEP instruc-

tion. Although the CPU is disabled, the peripherals

continue to be clocked from the primary clock source

specified in Configuration Register 1H. The OSTS bit

remains set in PRI_IDLE mode (see Figure 3-3).

When a wake event occurs, the CPU is clocked from

the primary clock source. A delay of approximately

μs is required between the wake event and code

execution starts. This is required to allow the CPU to

become ready to execute instructions. After the wake-

up, the OSTS bit remains set. The IDLEN and SCS bits

are not affected by the wake-up (see Figure 3-4).

FIGURE 3-3:

TRANSITION TIMING TO PRI_IDLE MODE

FIGURE 3-4:

TRANSITION TIMING FOR WAKE FROM PRI_IDLE MODE

Peripheral

Program

PC + 2

OSC1

CPU Clock

Clock

Counter

OSC1

Peripheral

Program

CPU Clock

PC + 2

Clock

Counter

Wake Event

CPU Start-up Delay

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