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AJAV-5601 bảng dữ liệu(PDF) 2 Page - AVAGO TECHNOLOGIES LIMITED |
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AJAV-5601 bảng dữ liệu(HTML) 2 Page - AVAGO TECHNOLOGIES LIMITED |
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2 / 6 page ![]() 2 Electrical Characteristics Table 1. Absolute Minimum and Maximum Ratings [1] Parameter Symbol Condition Min Typ Max Unit Supply Voltage [2] VBATT -0.3 - 4.5 V Control Voltage [3] VCTRL VCTRL < VBATT -0.3 - 4.5 V RF Input Power [4] - - +10 dBm Electrostatic Discharge (ESD) [5] Human Body Model (HBM) - - 3.0 kV Storage Temperature TSTG -55 - 125 °C Notes: 1. Permanent device damage may occur if the ratings above are exceeded. Functional operation is not guaranteed under these conditions and should be restricted to the recommended operating conditions in Table 2. Exposure to absolute ratings for extended periods may affect device reliability. 2. Supply voltage is applied to VBAT pin. 3. Control voltages are applied to VEN, VM0, VM1 pins. 4. RF input is applied to RFI, CPLI pins. 5. For all pins. Table 2. Operating Conditions [1] Parameter Symbol Condition Min Typ Max Unit Supply Voltage [2] VBATT 2.5 3.8 4.2 V Control Voltage – High [3] VIH VIH < VBATT 1.3 1.8 VBATT V Control Voltage – Low [3] VIL 0.0 - 0.5 V Ambient Temperature TA -30 25 90 °C Notes: 1. To ensure proper operation, the VEN pin should be asserted from VIL to VIH at least 2 ms after power is applied to the VBAT pin. 2. Device remains functional down to VBATT = 2.5 V. At VBATT < 3.4 V, output power is derated by 0.5 dB. 3. Logic states for VEN, VM0, VM1 pins. Table 3. Mode Control Logic [1] Mode Output Power Range [2] VEN VM0 VM1 High Power Mode (HP) 16.5 dBm < POUT ≤ PMAX High Low Low Mid Power Mode (MP) 6.0 dBm < POUT ≤ 16.5 dBm High High Low Low Power Mode (LP) POUT ≤ 6.0 dBm High High High Powerdown Low X X Notes: 1. The VM0 and VM1 pins are controlled externally to achieve maximum PA efficiency. High and low logic states are specified in Table 2. 2. Maximum linear output power, PMAX, is defined in Table 4. |
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