MC68HC908GR4MP datasheet(316/408 Pages) FREESCALE

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Serial Peripheral Interface (SPI)

Technical Data

MC68HC908GR8 — Rev 4.0

316

Serial Peripheral Interface (SPI)

MOTOROLA

The following sources in the SPI status and control register can generate

CPU interrupt requests:

•

SPI receiver full bit (SPRF) — The SPRF bit becomes set every

time a byte transfers from the shift register to the receive data

SPRF generates an SPI receiver/error CPU interrupt request.

•

SPI transmitter empty (SPTE) — The SPTE bit becomes set every

time a byte transfers from the transmit data register to the shift

SPTE generates an SPTE CPU interrupt request.

20.10 Resetting the SPI

Any system reset completely resets the SPI. Partial resets occur

whenever the SPI enable bit (SPE) is low. Whenever SPE is low, the

following occurs:

•

The SPTE flag is set.

•

Any transmission currently in progress is aborted.

•

The shift register is cleared.

•

The SPI state counter is cleared, making it ready for a new

complete transmission.

•

All the SPI port logic is defaulted back to being general-purpose

I/O.

These items are reset only by a system reset:

•

All control bits in the SPCR register

•

All control bits in the SPSCR register (MODFEN, ERRIE, SPR1,

and SPR0)

•

The status flags SPRF, OVRF, and MODF

By not resetting the control bits when SPE is low, the user can clear SPE

between transmissions without having to set all control bits again when

SPE is set back high for the next transmission.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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