MPC8349EVVALDB datasheet(69/87 Pages) FREESCALE

tên linh kiện	MPC8349EVVALDB

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MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13

Freescale Semiconductor

Clocking

As described in Section 19, “Clocking,” the LBIUCM, DDRCM, and SPMF parameters in the reset

configuration word low and the CFG_CLKIN_DIV configuration input signal select the ratio between the

primary clock input (CLKIN or PCI_CLK) and the internal coherent system bus clock (csb_clk). Table 59

and Table 60 show the expected frequency values for the CSB frequency for select csb_clk to

CLKIN/PCI_SYNC_IN ratios.

0111

× 7

1000

× 8

1001

× 9

1010

× 10

1011

× 11

1100

× 12

1101

× 13

1110

× 14

1111

× 15

Table 59. CSB Frequency Options for Host Mode

CFG_CLKIN_DIV

at Reset1

SPMF

csb_clk :

Input Clock Ratio2

Input Clock Frequency (MHz)2

16.67

33.33

66.67

csb_clk Frequency (MHz)

Low

0010

2 : 1

133

Low

0011

3 : 1

100

200

Low

0100

4 : 1

100

133

266

Low

0101

5 : 1

125

166

333

Table 58. System PLL Multiplication Factors (continued)

RCWL[SPMF]

System PLL Multiplication Factor

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