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23LCV1024 bảng dữ liệu(PDF) 10 Page - Microchip Technology

tên linh kiện 23LCV1024
Giải thích chi tiết về linh kiện  1 Mbit SPI Serial SRAM with Battery Backup and SDI Interface
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23LCV1024 bảng dữ liệu(HTML) 10 Page - Microchip Technology

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23LCV1024
DS25156A-page 10
Preliminary
 2012 Microchip Technology Inc.
2.5
Read Mode Register Instruction
(RDMR)
The Read Mode Register instruction (RDMR) provides
access to the MODE register. The MODE register may
be read at any time. The MODE register is formatted as
follows:
TABLE 2-2:
MODE REGISTER
The mode bits indicate the operating mode of the
SRAM. The possible modes of operation are:
0 0 = Byte mode
1 0 = Page mode
0 1 = Sequential mode (default operation)
1 1 = Reserved
Bits 0 through 5 are reserved and should always be set
to ‘0’.
See Figure 2-7 for the RDMR timing sequence.
FIGURE 2-7:
READ MODE REGISTER TIMING SEQUENCE (RDMR)
76
5
4
3
2
1
0
W/R
W/R
–
–
–
–
–
–
MODE MODE
00
0
0
0
0
W/R = writable/readable
SO
SI
CS
9
1011
12131415
11
0
0
0
0
00
76
5
4
2
1
0
Instruction
Data from MODE Register
High-Impedance
SCK
0
2
34
56
7
1
8
3



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