AD9512 datasheet(12/48 Pages) AD

12 / 48 page

AD9512

Rev. A | Page 12 of 48

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

DELAY BLOCK ADDITIVE TIME JITTER1

Incremental additive jitter1

100 MHz Output

Delay FS = 1 ns (1600 μA, 1C) Fine Adj. 00000

0.61

Delay FS = 1 ns (1600 μA, 1C) Fine Adj. 11111

0.73

Delay FS = 2 ns (800 μA, 1C) Fine Adj. 00000

0.71

Delay FS = 2 ns (800 μA, 1C) Fine Adj. 11111

1.2

Delay FS = 3 ns (800 μA, 4C) Fine Adj. 00000

0.86

Delay FS = 3 ns (800 μA, 4C) Fine Adj. 11111

1.8

Delay FS = 4 ns (400 μA, 4C) Fine Adj. 00000

1.2

Delay FS = 4 ns (400 μA, 4C) Fine Adj. 11111

2.1

Delay FS = 5 ns (200 μA, 1C) Fine Adj. 00000

1.3

Delay FS = 5 ns (200 μA, 1C) Fine Adj. 11111

2.7

Delay FS = 11 ns (200 μA, 4C) Fine Adj. 00000

2.0

Delay FS = 11 ns (200 μA, 4C) Fine Adj. 00100

2.8

1 This value is incremental. That is, it is in addition to the jitter of the LVDS or CMOS output without the delay. To estimate the total jitter, the LVDS or CMOS output jitter

should be added to this value using the root sum of the squares (RSS) method.

SERIAL CONTROL PORT

Table 6.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

CSB, SCLK (INPUTS)

CSB and SCLK have 30 kΩ

internal pull-down resistors

Input Logic 1 Voltage

2.0

Input Logic 0 Voltage

0.8

Input Logic 1 Current

110

μA

Input Logic 0 Current

μA

Input Capacitance

SDIO (WHEN INPUT)

Input Logic 1 Voltage

2.0

Input Logic 0 Voltage

0.8

Input Logic 1 Current

Input Logic 0 Current

Input Capacitance

SDIO, SDO (OUTPUTS)

Output Logic 1 Voltage

2.7

Output Logic 0 Voltage

0.4

TIMING

Clock Rate (SCLK, 1/tSCLK)

MHz

Pulse Width High, tPWH

Pulse Width Low, tPWL

SDIO to SCLK Setup, tDS

SCLK to SDIO Hold, tDH

SCLK to Valid SDIO and SDO, tDV

CSB to SCLK Setup and Hold, tS, tH

CSB Minimum Pulse Width High, tPWH

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