AD9512BCPZ datasheet(45/48 Pages) AD

45 / 48 page

AD9512

Rev. A | Page 45 of 48

Because of the limitations of single-ended CMOS clocking,

consider using differential outputs when driving high speed

signals over long traces. The AD9512 offers both LVPECL and

LVDS outputs, which are better suited for driving long traces

where the inherent noise immunity of differential signaling

provides superior performance for clocking converters.

LVDS CLOCK DISTRIBUTION

Low voltage differential signaling (LVDS) is a second

differential output option for the AD9512. LVDS uses a current

mode output stage with several user-selectable current levels.

The normal value (default) for this current is 3.5 mA, which

yields 350 mV output swing across a 100 Ω resistor. The LVDS

outputs meet or exceed all ANSI/TIA/EIA—644 specifications.

LVPECL CLOCK DISTRIBUTION

The low voltage, positive emitter-coupled, logic (LVPECL)

outputs of the AD9512 provide the lowest jitter clock signals

available from the AD9512. The LVPECL outputs (because they

are open emitter) require a dc termination to bias the output

transistors. A simplified equivalent circuit in Figure 27 shows

the LVPECL output stage.

A recommended termination circuit for the LVDS outputs is

shown in Figure 44.

3.3V

LVDS

100

DIFFERENTIAL (COUPLED)

3.3V

LVDS

100

In most applications, a standard LVPECL far-end termination is

recommended, as shown in Figure 42. The resistor network is

designed to match the transmission line impedance (50 Ω) and

the desired switching threshold (1.3 V).

Figure 44. LVDS Output Termination

3.3V

LVPECL

SINGLE-ENDED

(NOT COUPLED)

3.3V

LVPECL

127

VT = VCC – 1.3V

See Application Note AN-586 on the ADI website at

www.analog.com for more information on LVDS.

POWER AND GROUNDING CONSIDERATIONS AND

POWER SUPPLY REJECTION

Many applications seek high speed and performance under less

than ideal operating conditions. In these application circuits,

the implementation and construction of the PCB is as

important as the circuit design. Proper RF techniques must be

used for device selection, placement, and routing, as well as for

power supply bypassing and grounding to ensure optimum

performance.

Figure 42. LVPECL Far-End Termination

3.3V

LVPECL

DIFFERENTIAL

(COUPLED)

3.3V

LVPECL

100

0.1nF

200

Figure 43. LVPECL with Parallel Transmission Line

AD9512BCPZ bảng dữ liệu(PDF) 45 Page - Analog Devices

AD9512BCPZ bảng dữ liệu(HTML) 45 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48

bảng dữ liệu tải về

Link URL