74LVC1G08

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© NXP B.V. 2012. All rights reserved.

Product data sheet

Rev. 10 — 29 June 2012

2 of 19

NXP Semiconductors

74LVC1G08

Single 2-input AND gate

3.

Ordering information

4.

Marking

[1]

The pin 1 indicator is located on the lower left corner of the device, below the marking code.

5.

Functional diagram

Table 1.

Ordering information

Type number

Package

Temperature

range

Name

Description

Version

74LVC1G08GW

40 Cto+125 C

TSSOP5

plastic thin shrink small outline package; 5 leads;

body width 1.25 mm

SOT353-1

74LVC1G08GV

40 Cto+125 C

SC-74A

plastic surface-mounted package; 5 leads

SOT753

74LVC1G08GM

40 Cto+125 C

XSON6

plastic extremely thin small outline package;

no leads; 6 terminals; body 1

 1.45  0.5 mm

SOT886

74LVC1G08GF

40 C to +125 C

XSON6

plastic extremely thin small outline package;

no leads; 6 terminals; body 1

 1  0.5 mm

SOT891

74LVC1G08GN

40 C to +125 C

XSON6

extremely thin small outline package; no leads;

6 terminals; body 0.9

 1.0  0.35 mm

SOT1115

74LVC1G08GS

40 C to +125 C

XSON6

extremely thin small outline package; no leads;

6 terminals; body 1.0

 1.0  0.35 mm

SOT1202

74LVC1G08GX

40 C to +125 C

X2SON5

X2SON5: plastic thermal enhanced extremely thin

small outline package; no leads; 5 terminals;

body 0.8

 0.8  0.35 mm

SOT1226

Table 2.

Marking

Type number

Marking code[1]

74LVC1G08GW

VE

74LVC1G08GV

V08

74LVC1G08GM

VE

74LVC1G08GF

VE

74LVC1G08GN

VE

74LVC1G08GS

VE

74LVC1G08GX

VE

Fig 1.

Logic symbol

Fig 2.

IEC logic symbol

Fig 3.

Logic diagram

mna113

B

A

Y

2

1

4

mna114

2

4

&

1

mna221

A

B

Y