AD9779A-EBZ datasheet(7/56 Pages) AD

7 / 56 page

AD9776A/AD9778A/AD9779A

Rev. B | Page 7 of 56

DIGITAL INPUT DATA TIMING SPECIFICATIONS

All modes, −40°C to +85°C.

Table 3.

Parameter

Conditions

Min

Typ

Max

Unit

INPUT DATA1

Setup Time

Input data to DATACLK

3.0

Hold Time

Input data to DATACLK

−0.05

Setup Time

Input data to REFCLK

−0.80

Hold Time

Input data to REFCLK

3.80

LATENCY

1× Interpolation

With or without modulation

DACCLK cycles

2× Interpolation

With or without modulation

DACCLK cycles

4× Interpolation

With or without modulation

146

DACCLK cycles

8× Interpolation

With or without modulation

297

DACCLK cycles

Inverse Sync

DACCLK cycles

3-WIRE INTERFACE

Maximum Clock Rate (SCLK)

MHz

Minimum Pulse Width High, tPWH

12.5

Minimum Pulse Width Low, tPWL

12.5

Setup Time, tDS

SDIO to SCLK

2.8

Hold Time, tDH

SDIO to SCLK

0.0

Setup Time, tDS

CSB to SCLK

2.8

Data Valid, tDV

SDO to SCLK

2.0

POWER-UP TIME2

260

RESET

Minimum Pulse Width, High

DACCLK cycles

1 Specified values are with PLL disabled. Timing vs. temperature and data valid keep out windows (that is, the minimum amount of time valid data must be presented to

the device to ensure proper sampling) are delineated in Table 28.

2 Measured from CSB rising edge when Register 0x00, Bit 4, is written from 1 to 0 with the VREF decoupling capacitor equal to 0.1 μF.

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