AD9854ASVZ datasheet(28/52 Pages) AD

28 / 52 page

AD9854

Rev. E | Page 28 of 52

h, it

s phase

put carrier.

o Phase

ster 2.

Activate the I/O update clock when ready.

using the serial or high speed parallel programming bus.

•

Continue chirp by immediately returning to the beginning

frequency (F1) in a sawtooth fashion, and then repeating the

previous chirp process using the CLR ACC1 control bit.

An automatic, repeating chirp can be set up by using the

32-bit update clock to issue the CLR ACC1 command at

precise time intervals. Adjusting the timing intervals or

changing the delta frequency word changes the chirp

range. It is incumbent upon the user to balance the chirp

duration and frequency resolution to achieve the proper

frequency range.

BPSK (Mode 100)

Binary, biphase, or bipolar phase shift keying is a means to

rapidly select between two preprogrammed 14-bit output phase

offsets that equally affect both the I and Q outputs of the

AD9854. The logic state of Pin 29, the BPSK pin, controls the

selection of Phase Adjust Register 1 or Phase Adjust Register 2.

When low, Pin 29 selects Phase Adjust Register 1; when hig

selects Phase Adjust Register 2. Figure 48 illustrate

changes made to four cycles of an out

Basic BPSK Programming Steps

Program a carrier frequency into Frequency Tuning Word 1.

Program the appropriate 14-bit phase words int

Adjust Register 1 and Phase Adjust Regi

Attach the BPSK data source to Pin 29.

Note that for higher-order PSK modulation, the user can sele

the single-tone mode and program Phase Adjust Register

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