TMP411

SBOS383C − DECEMBER 2006 − REVISED MAY 2008

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18

Frame 1 Two−Wire Slave Address Byte

Frame 2 Pointer Register Byte

Frame 4 Data Byte 2

1

Start By

Master

ACK By

TMP411A

ACK By

TMP411A

ACK By

TMP411A

Stop By

Master

19

1

1

D7

D6

D5

D4

D3

D2

D1

D0

9

Frame3DataByte 1

ACK By

TMP411A

1

D7

SDA

(Continued)

SCL

(Continued)

D6

D5

D4

D3

D2

D1

D0

9

9

SDA

SCL

00

1

1

0

R/W

P7

P6

P5P4

P3P2

P1P0

…

…

NOTE (1): Slave address 1001100 (TMP411A) shown. Slave address changes for TMP411B and TMP411C. See Ordering Information table for more details.

Figure 14. Two-Wire Timing Diagram for Write Word Format

Frame1Two−Wire Slave Address Byte

Frame 2 Pointer Register Byte

1

Start By

Master

ACK By

TMP411A

ACK By

TMP411A

Frame3Two−Wire Slave Address Byte

Frame4 Data Byte1ReadRegister

Start By

Master

ACK By

TMP411A

NACK By

Master

(2)

From

TMP411A

19

1

9

19

1

9

SDA

SCL

00

1

R/W

P7

P6

P5

P4

P3

P2

P1

P0

SDA

(Continued)

SCL

(Continued)

10

0

1

10

0

(1)

10

0

(1)

R/W

D7

D6

D5

D4

D3

D2

D1

D0

(1) Slave address 1001100 (TMP411A) shown. Slave address changes for TMP411B and TMP411C. See Ordering Information table for more details.

(2) Master should leave SDA high to terminate a single−byte read operation.

NOTES:

Figure 15. Two-Wire Timing Diagram for Single-Byte Read Format