EP2C8 datasheet(28/36 Pages) ALTERA

28 / 36 page

Page 28

IEEE Std. 1149.1 (JTAG) Boundary-Scan

Enhanced Configuration (EPC) Devices Datasheet

January 2012

Altera Corporation

You can also program the EPC devices using the Quartus II software, the Altera

Programming Unit (APU), and the appropriate configuration device programming

adapter. Table 12 lists which programming adapter to use with each EPC device.

IEEE Std. 1149.1 (JTAG) Boundary-Scan

The EPC device provides JTAG BST circuitry that complies with the IEEE Std.

1149.1-1990 specification. JTAG BST can be performed before or after configuration,

but not during configuration.

Figure 6 shows the timing requirements for the JTAG signals.

Table 13 lists the timing parameters and values for the EPC device.

Table 12. Programming Adapters

Device

Package

Adapter

EPC16

88-pin UFBGA

PLMUEPC-88

100-pin PQFP

PLMQEPC-100

EPC8

100-pin PQFP

PLMQEPC-100

EPC4

100-pin PQFP

PLMQEPC-100

Figure 6. JTAG Timing Waveforms

TDO

TCK

tJPZX

tJPCO

tJPH

tJPXZ

tJCP

tJPSU

tJCL

tJCH

TDI

TMS

Signal

to be

Captured

Signal

to be

Driven

tJSZX

tJSSU

tJSH

tJSCO

tJSXZ

Table 13. JTAG Timing Parameters and Values (Part 1 of 2)

Symbol

Parameter

Min

Max

Unit

tJCP

TCK

clock period

100

—

tJCH

TCK

clock high time

—

tJCL

TCK

clock low time

—

tJPSU

JTAG port setup time

—

tJPH

JTAG port hold time

—

tJPCO

JTAG port clock output

—

tJPZX

JTAG port high impedance to valid output

—

EP2C8 bảng dữ liệu(PDF) 28 Page - Altera Corporation

EP2C8 bảng dữ liệu(HTML) 28 Page - Altera Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

bảng dữ liệu tải về

Link URL