POWER-ON

RESET

DAC

REGISTER

INPUT

CONTROL

LOGIC

8-BIT DAC

8

8

POWER-DOWN

CONTROL

LOGIC

BUFFER

1k

100k

SCLK

SYNC

REF(+) REF(-)

GND

DAC081S101

SCLK

GND

1

2

3

6

5

4

SYNC

1

2

3

4

8

7

6

5

GND

SCLK

NC

NC

SYNC

DAC081S101

SNAS323C – JUNE 2005 – REVISED FEBRUARY 2013

www.ti.com

Pin Configuration

SOT

VSSOP

Block Diagram

Pin Descriptions

SOT-23

VSSOP

Name

Description

Pin No.

Pin No.

1

4

DAC Analog Output Voltage.

GND

2

8

Ground reference for all on-chip circuitry.

3

1

Power supply and Reference input. Should be decoupled to GND.

Serial Data Input. Data is clocked into the 16-bit shift register on the falling

4

7

edges of SCLK after the fall of SYNC.

Serial Clock Input. Data is clocked into the input shift register on the falling

SCLK

5

6

edges of this pin.

Frame synchronization input for the data input. When this pin goes low, it

enables the input shift register and data is transferred on the falling edges

SYNC

6

5

of SCLK. The DAC is updated on the 16th clock cycle unless SYNC is

brought high before the 16th clock, in which case the rising edge of SYNC

acts as an interrupt and the write sequence is ignored by the DAC.

NC

2, 3

No Connect. There is no internal connection to these pins.

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

2

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