IMX6DQAEC datasheet(21/165 Pages) FREESCALE

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Electrical Characteristics

i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2.3

Freescale Semiconductor

GPIO supplies8

NVCC_CSI,

NVCC_EIM0,

NVCC_EIM1,

NVCC_EIM2,

NVCC_ENET,

NVCC_GPIO,

NVCC_LCD,

NVCC_NANDF,

NVCC_SD1,

NVCC_SD2,

NVCC_SD3,

NVCC_JTAG

1.65

1.8,

2.8,

3.3

3.6

Isolation between the NVCC_EIMx and

NVCC_SDx different supplies allow them to

operate at different voltages within the specified

range.

Example: NVCC_EIM1 can operate at 1.8 V

while NVCC_EIM2 operates at 3.3 V.

NVCC_LVDS_2P59

NVCC_MIPI

2.25

2.5

2.75

—

HDMI supply voltages

HDMI_VP

0.99

1.1

1.3

—

HDMI_VPH

2.25

2.5

2.75

—

PCIe supply voltages

PCIE_VP

1.023

1.1

1.3

—

PCIE_VPH

2.325

2.5

2.75

—

PCIE_VPTX

1.023

1.1

1.3

—

SATA Supply voltages

SATA_VP

0.99

1.1

1.3

—

SATA_VPH

2.25

2.5

2.75

—

Junction temperature

-40

125

CSee i.MX 6Dual/6Quad Product Lifetime Usage

Estimates Application Note, AN4724, for

information on product lifetime (power-on

years) for this processor.

1 Applying the maximum voltage results in maximum power consumption and heat generation. Freescale recommends a voltage

set point = (Vmin + the supply tolerance). This results in an optimized power/speed ratio.

2 For Quad core system, connect to VDD_ARM_IN. For Dual core system, may be shorted to GND together with

VDD_ARM23_CAP to reduce leakage.

3 VDD_ARM_IN and VDD_SOC_IN must be at least 125 mV higher than the LDO Output Set Point for correct voltage regulation.

4 VDD_ARM_CAP must not exceed VDD_CACHE_CAP by more than +50 mV. VDD_CACHE_CAP must not exceed

VDD_ARM_CAP by more than 200 mV.

5 VDD_SOC_CAP and VDD_PU_CAP must be equal.

6 VDDSOC and VDDPU output voltages must be set according to this rule: VDDARM-VDDSOC/PU<50mV.

7 While setting VDD_SNVS_IN voltage with respect to Charging Currents and RTC, see the Hardware Development Guide for

i.MX 6Dual, 6Quad, 6Solo, 6DualLite Families of Applications Processors (IMX6DQ6SDLHDG).

8 All digital I/O supplies (NVCC_xxxx) must be powered under normal conditions whether the associated I/O pins are in use or

not, and associated I/O pins need to have a pull-up or pull-down resistor applied to limit any floating gate current.

9 This supply also powers the pre-drivers of the DDR I/O pins; therefore, it must always be provided, even when LVDS is not used.

Table 6. Operating Ranges (continued)

Parameter

Description

Symbol

Min

Typ

Max1

Unit

Comment

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