OP196 datasheet(39/88 Pages) AD

39 / 88 page

ADuC841/ADuC842/ADuC843

Rev. 0 | Page 39 of 88

Using the DAC

The on-chip DAC architecture consists of a resistor string DAC

followed by an output buffer amplifier, the functional equivalent

of which is illustrated in Figure 42. Details of the actual DAC

architecture can be found in U.S. Patent Number 5969657

(www.uspto.gov). Features of this architecture include inherent

guaranteed monotonicity and excellent differential linearity.

OUTPUT

BUFFER

HIGH Z

DISABLE

(FROM MCU)

DAC0

ADuC841/ADuC842

AVDD

VREF

Figure 42. Resistor String DAC Functional Equivalent

As shown in Figure 42, the reference source for each DAC is

user selectable in software. It can be either AVDD or VREF. In

0 V-to-AVDD mode, the DAC output transfer function spans

from 0 V to the voltage at the AVDD pin. In 0 V-to-VREF mode,

the DAC output transfer function spans from 0 V to the internal

VREF or, if an external reference is applied, the voltage at the CREF

pin. The DAC output buffer amplifier features a true rail-to-rail

output stage implementation. This means that unloaded, each

output is capable of swinging to within less than 100 mV of

both AVDD and ground. Moreover, the DAC’s linearity specifica-

tion (when driving a 10 kΩ resistive load to ground) is guaranteed

through the full transfer function except Codes 0 to 100, and, in

0 V-to-AVDD mode only, Codes 3995 to 4095. Linearity degrada-

tion near ground and VDD is caused by saturation of the output

amplifier, and a general representation of its effects (neglecting

offset and gain error) is illustrated in Figure 43. The dotted line

in Figure 43 indicates the ideal transfer function, and the solid

line represents what the transfer function might look like with

endpoint nonlinearities due to saturation of the output amplifier.

Note that Figure 43 represents a transfer function in 0 V-to-VDD

mode only. In 0 V-to-VREF mode (with VREF < VDD), the lower

nonlinearity would be similar, but the upper portion of the

transfer function would follow the ideal line right to the end

(VREF in this case, not VDD), showing no signs of endpoint

linearity errors.

VDD

VDD–50mV

VDD–100mV

100mV

50mV

0mV

000H

FFFH

Figure 43. Endpoint Nonlinearities Due to Amplifier Saturation

SOURCE/SINK CURRENT (mA)

DAC LOADED WITH 0000H

DAC LOADED WITH 0FFFH

Figure 44. Source and Sink Current Capability with VREF = VDD = 5 V

SOURCE/SINK CURRENT (mA)

DAC LOADED WITH 0000H

DAC LOADED WITH 0FFFH

Figure 45. Source and Sink Current Capability with VREF = VDD = 3 V

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